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PIC16F/LF1826/27 Data Sheet
18/20/28-Pin Flash Microcontrollers with nanoWatt XLP Technology
2010 Microchip Technology Inc.
Preliminary
DS41391C
Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-285-4
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS41391C-page 2
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1826/27
18/20/28-Pin Flash Microcontrollers with nanoWatt XLP Technology
High-Performance RISC CPU:
* C Compiler Optimized Architecture * 256 bytes Data EEPROM * Up to 4 Kbytes Linear Program Memory Addressing * Up to 384 bytes Linear Data Memory Addressing * Interrupt Capability with Automatic Context Saving * 16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset * Direct, Indirect and Relative Addressing modes: - Two full 16-bit File Select Registers (FSRs) - FSRs can read program and data memory
Extreme Low-Power Management PIC16LF1826/27 with nanoWatt XLP:
* Sleep mode: 30 nA * Watchdog Timer: 500 nA * Timer1 Oscillator: 600 nA @ 32 kHz
Analog Features:
* Analog-to-Digital Converter (ADC) Module: - 10-bit resolution, 12 channels - Auto acquisition capability - Conversion available during Sleep * Analog Comparator Module: - Two rail-to-rail analog comparators - Power mode control - Software controllable hysteresis * Voltage Reference Module: - Fixed Voltage Reference (FVR) with 1.024V, 2.048V and 4.096V output levels - 5-bit rail-to-rail resistive DAC with positive and negative reference selection
Flexible Oscillator Structure:
* Precision 32 MHz Internal Oscillator Block: - Factory calibrated to 1%, typical - Software selectable frequencies range of 31 kHz to 32 MHz * 31 kHz Low-Power Internal Oscillator * Four Crystal modes up to 32 MHz * Three External Clock modes up to 32 MHz * 4X Phase Lock Loop (PLL) * Fail-Safe Clock Monitor: - Allows for safe shutdown if peripheral clock stops * Two-Speed Oscillator Start-up * Reference Clock Module: - Programmable clock output frequency and duty-cycle
Peripheral Highlights:
* 15 I/O Pins and 1 Input Only Pin: - High current sink/source 25 mA/25 mA - Programmable weak pull-ups - Programmable interrupt-on- change pins * Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler * Enhanced Timer1: - 16-bit timer/counter with prescaler - External Gate Input mode - Dedicated, low-power 32 kHz oscillator driver * Up to three Timer2-types: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler * Up to two Capture, Compare, PWM (CCP) Modules * Up to two Enhanced CCP (ECCP) Modules: - Software selectable time bases - Auto-shutdown and auto-restart - PWM steering * Up to two Master Synchronous Serial Port (MSSP) with SPI and I2CTM with: - 7-bit address masking - SMBus/PMBusTM compatibility * Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) Module * mTouchTM Sensing Oscillator Module: - Up to 12 input channels * Data Signal Modulator Module: - Selectable modulator and carrier sources * SR Latch: - Multiple Set/Reset input options - Emulates 555 Timer applications
Special Microcontroller Features:
* * * * * * * * * * * 1.8V-5.5V Operation - PIC16F1826/27 1.8V-3.6V Operation - PIC16LF1826/27 Self-Programmable under Software Control Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) Programmable Brown-out Reset (BOR) Extended Watchdog Timer (WDT): - Programmable period from 1ms to 268s Programmable Code Protection In-Circuit Serial ProgrammingTM (ICSPTM) via two pins In-Circuit Debug (ICD) via two pins Enhance Low-Voltage Programming Power-Saving Sleep mode
2010 Microchip Technology Inc.
Preliminary
DS41391C-page 3
PIC16F/LF1826/27
PIC16F/LF1826/27 Family Types
ECCP (Half-Bridge) ECCP (Full-Bridge) Timers (8/16-bit) 10-bit ADC (ch) CapSense (ch) Comparators Program Memory Device Words Data Memory Data EEPROM (bytes) I/O's(1) SRAM (bytes)
PIC16LF1826 2K 256 PIC16F1826 2K 256 PIC16LF1827 4K 384 PIC16F1827 4K 384 Note 1: One pin is input only.
256 256 256 256
16 16 16 16
12 12 12 12
12 12 12 12
2 2 2 2
2/1 2/1 4/1 4/1
1 1 1 1
1 1 2 2
1 1 1 1
-- -- 1 1
-- -- 2 2
Yes Yes Yes Yes
DS41391C-page 4
Preliminary
2010 Microchip Technology Inc.
SR Latch
EUSART
MSSP
CCP
Pin Diagram - 18-Pin PDIP, SOIC (PIC16F/LF1826/27)
PDIP, SOIC RA2/AN2/CPS2/C12IN2-/C12IN+/VREF-/DACOUT RA3/AN3/CPS3/C12IN3-/C1IN+/VREF+/C1OUT/CCP3(2)/SRQ RA4/AN4/CPS4/C2OUT/T0CKI/CCP4(2)/SRNQ RA5/MCLR/VPP/SS1(1,2) VSS RB0/SRI/T1G/CCP1 /P1A /INT/SRI/FLT0 RB1/AN11/CPS11/RX(1)/DT(1)/SDA1/SDI1 RB2/AN10/CPS10/MDMIN/TX /CK /RX /DT /SDA2 /SDI2 /SDO1
(1) (1) (1) (1) (2) (2) (1) (1) (1)
2010 Microchip Technology Inc.
1 2 3 4 5 6 7 8 9 PIC16F/LF1826/27
18 17 16 15 14 13 12 11 10
RA1/AN1/CPS1/C12IN1-/SS2(2) RA0/AN0/CPS0/C12IN0-/SDO2(2) RA7/OSC1/CLKIN/P1C(1)/CCP2(1,2)/P2A(1,2) RA6/OSC2/CLKOUT/CLKR/P1D(1)/P2B(1,2)/SDO1(1) VDD RB7/AN6/CPS6/T1OSO/P1D(1)/P2B(1,2)/MDCIN1/ICSPDAT RB6/AN5/CPS5/T1CKI/T1OSI/P1C(1)/CCP2(1,2)/P2A(1,2)/ICSPCLK RB5/AN7/CPS7/P1B/TX(1)/CK(1)/SCL2(2)/SCK2(2)/SS1(1) RB4/AN8/CPS8/SCL1/SCK1/MDCIN2
RB3/AN9/CPS9/MDOUT/CCP1(1)/P1A(1)
Note
1: 2:
Pin feature is dependent on device configuration. ECCP2, CCP3, CCP4, MSSP2 functions are only available on the PIC16F/LF1827.
Preliminary
DS41391C-page 5
Pin Diagram - 20-Pin SSOP (PIC16F/LF1826/27)
SSOP RA2/AN2/CPS2/C12IN2-/C12IN+/VREF-/DACOUT RA3/AN3/CPS3/C12IN3-/C1IN+/VREF+/C1OUT/CCP3(2)/SRQ RA4/AN4/CPS4/C2OUT/T0CKI/CCP4(2)/SRNQ RA5/MCLR/VPP/SS1(1,2) VSS VSS RB0/SRI/T1G/CCP1 /P1A /INT/FLT0 RB1/AN11/CPS11/RX
(1,3)/DT(1,3)/SDA1/SDI1 (1) (1)
1 2 3 PIC16F/LF1826/27 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
RA1/AN1/CPS1/C12IN1-/SS2(2)
PIC16F/LF1826/27
RA0/AN0/CPS0/C12IN0-/SDO2(2) RA7/OSC1/CLKIN/P1C(1)/CCP2(1,2)/P2A(1,2) RA6/OSC2/CLKOUT/CLKR/P1D(1)/P2B(1,2)/SDO1(1) VDD VDD RB7/AN6/CPS6/T1OSO/P1D(1)/P2B(1,2)/MDCIN1/ICSPDAT RB6/AN5/CPS5/T1CKI/T1OSI/P1C(1,3)/CCP2(1,2)/P2A(1,2)/ICSPCLK RB5/AN7/CPS7/P1B/TX(1)/CK(1)/SCL2(2)/SCK2(2)/SS1(1) RB4/AN8/CPS8/SCL1/SCK1/MDCIN2
RB2/AN10/CPS10/MDMIN/TX(1,3)/CK(1,3)/RX(1)/DT(1)/SDA2(2)/SDI2(2)/SDO1(1,3) RB3/AN9/CPS9/MDOUT/CCP1 /P1A
(1) (1)
Note
1: 2:
Pin feature is dependent on device configuration. ECCP2, CCP3, CCP4, MSSP2 functions are only available on the PIC16F/LF1827.
PIC16F/LF1826/27
Pin Diagram - 28-Pin QFN/UQFN (PIC16F/LF1826/27)
QFN/UQFN
RA3/AN3/CPS3/C12IN3-/C1IN+/VREF+/C1OUT/CCP3(2)/SRQ RA2/AN2/CPS2/C12IN2-/C12IN+/VREF-/DACOUT
RA4/AN4/CPS4/C2OUT/T0CKI/CCP4(2)/SRNQ
RA1/AN1/CPS1/C12IN1-/SS2(2) RA0/AN0/CPS0/C12IN0-/SDO2(2) NC NC
RA5/ MCLR/VPP/SS1(1) NC VSS NC VSS NC RB0/SRI/T1G/CCP1(1)/P1A(1)/INT/SRI/FLT0
28 27 26 25 24 23 22
NC
RB1/AN11/CPS11/RX(1)/DT(1)/SDA1/SDI1
RB2/AN10/CPS10/MDMIN/TX(1)/CK(1)/RX(1)/DT(1)/SDA2(2)/SDI2(2)/SDO1(1)
RB3/AN9/CPS9/MDOUT/CCP1(1)/P1A(1)
RB4/AN8/CPS8/SCL1/SCK1/MDCIN2
Note
1: 2:
Pin feature is dependent on device configuration. ECCP2, CCP3, CCP4, MSSP2 functions are only available on the PIC16F/LF1827.
DS41391C-page 6
Preliminary
RB5/AN7/CPS7/P1B/TX /CK /SCL2 /SCK2 /SS1
(1)
(1)
(2)
(2)
(1)
NC
8 9 10 11 12 13 14
1 21 2 20 3 19 4 PIC16F/LF1826/27 18 17 5 6 16 7 15
RA7/OSC1/CLKIN/P1C(1)/CCP2(1,2)/P2A(1,2) RA6/OSC2/CLKOUT/CLKR/P1D(1)/P2B(1,2)/SDO1(1) VDD NC VDD RB7/AN6/CPS6/T1OSO/P1D(1)/P2B(1,2)/MDCIN1/ICSPDAT RB6/AN5/CPS5/T1CKI/T1OSI/P1C(1)/CCP2(1,2)/P2A(1,2)/ICSPCLK
2010 Microchip Technology Inc.
TABLE 1:
18-Pin PDIP/SOIC
18/20/28-PIN SUMMARY (PIC16F/LF1826/27)
28-Pin QFN/UQFN 20-Pin SSOP Comparator Cap Sense Reference Modulator SR Latch EUSART Interrupt ANSEL Pull-up Timers
2010 Microchip Technology Inc.
MSSP
Basic
CCP
A/D
RA0 RA1 RA2 RA3
RA4 RA5 RA6
RA7
I/O
17 18 1 2
19 20 1 2
23 24 26 27
Y Y Y Y
AN0 AN1 AN2 AN3
-- -- VREFDACOUT VREF+
CPS0 CPS1 CPS2 CPS3
C12IN0C12IN1C12IN2C12IN+ C12IN3C1IN+ C1OUT C2OUT -- --
-- -- -- SRQ
-- -- -- --
-- -- -- CCP3(2)
-- -- -- --
SDO2(2) SS2(2) -- --
-- -- -- --
-- -- -- --
N N N N
-- -- -- --
3 4 15
3 4 17
28 1 20
Y N N
AN4 -- --
-- -- --
CPS4 -- --
SRNQ -- --
T0CKI -- --
CCP4(2) -- P1D(1) P2B(1,2) P1C(1) CCP2(1,2) P2A(1,2) CCP1(1) P1A(1) FLT0 -- --
-- -- --
-- SS1(1) SDO1(1)
-- -- --
-- -- --
N Y(3) N
-- MCLR, VPP OSC2 CLKOUT CLKR OSC1 CLKIN --
16
18
21
N
--
--
--
--
--
--
--
--
--
--
N
Preliminary
DS41391C-page 7
RB0
6
7
7
N
--
--
--
--
SRI
T1G
--
--
INT IOC IOC IOC
--
Y
RB1 RB2
7 8
8 9
8 9
Y Y
AN11 AN10
-- --
CPS11 CPS10
-- --
-- --
-- --
RX(1,4) DT(1,4) RX(1),DT(1) TX(1,4) CK(1,4) -- -- TX(1) CK(1) --
SDA1 SDI1 SDA2(2) SDI2(2) SDO1(1,4) -- SCL1 SCK1 SCL2(2) SCK2(2) SS1(1,4) --
-- MDMIN
Y Y
-- --
PIC16F/LF1826/27
RB3 RB4 RB5
9 10 11
10 11 12
10 12 13
Y Y Y
AN9 AN8 AN7
-- -- --
CPS9 CPS8 CPS7
-- -- --
-- -- --
-- -- --
CCP1(1,4) P1A(1,4) -- P1B
IOC IOC IOC
MDOUT MDCIN2 --
Y Y Y
-- -- --
RB6
12
13
15
Y
AN5
--
CPS5
--
--
T1CKI T1OSI T1OSO -- --
P1C(1,4) CCP2(1,2,4) P2A(1,2,4) P1D(1,4) P2B(1,2,4) -- --
IOC
--
Y
ICSPCLK/ ICDCLK ICSPDAT/ ICDDAT VDD VSS
RB7 VDD Vss Note 1: 2: 3: 4:
13 14 5
14
16
Y -- --
AN6 -- --
-- -- --
CPS6 -- --
-- -- --
-- -- --
-- -- --
-- -- --
IOC -- --
MDCIN1 -- --
Y -- --
15,16 17,19 5,6 3,5
Pin functions can be moved using the APFCON0 or APFCON1 register. Functions are only available on the PIC16F/LF1827. Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control. Default function location.
PIC16F/LF1826/27
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 17 3.0 Memory Organization ................................................................................................................................................................. 19 4.0 Device Configuration .................................................................................................................................................................. 49 5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 55 6.0 Reference Clock Module ............................................................................................................................................................ 73 7.0 Resets ........................................................................................................................................................................................ 77 8.0 Interrupts .................................................................................................................................................................................... 85 9.0 Power-Down Mode (Sleep) ...................................................................................................................................................... 101 10.0 Watchdog Timer (WDT) ........................................................................................................................................................... 103 11.0 Data EEPROM and Flash Program Memory Control ............................................................................................................... 107 12.0 I/O Ports ................................................................................................................................................................................... 121 13.0 Interrupt-on-Change ................................................................................................................................................................. 133 14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 137 15.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 139 16.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 153 17.0 SR Latch................................................................................................................................................................................... 159 18.0 Comparator Module.................................................................................................................................................................. 165 19.0 Timer0 Module ......................................................................................................................................................................... 175 21.0 Timer1 Module ......................................................................................................................................................................... 179 22.0 Timer2/4/6 Modules.................................................................................................................................................................. 191 23.0 Data Signal Modulator (DSM) .................................................................................................................................................. 195 24.0 Capture/Compare/PWM (ECCP1, ECCP2, ECCP3, CCP4) Modules...................................................................................... 205 25.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 233 26.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 287 27.0 Capacitive Sensing Module ...................................................................................................................................................... 317 28.0 In-Circuit Serial ProgrammingTM (ICSPTM) ................................................................................................................................ 325 29.0 Instruction Set Summary .......................................................................................................................................................... 329 30.0 Electrical Specifications............................................................................................................................................................ 343 31.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 377 32.0 Development Support............................................................................................................................................................... 379 33.0 Packaging Information.............................................................................................................................................................. 383 Appendix A: Revision History............................................................................................................................................................. 393 Appendix B: Device Differences......................................................................................................................................................... 393 Index .................................................................................................................................................................................................. 395 The Microchip Web Site ..................................................................................................................................................................... 403 Customer Change Notification Service .............................................................................................................................................. 403 Customer Support .............................................................................................................................................................................. 403 Reader Response .............................................................................................................................................................................. 404 Product Identification System............................................................................................................................................................. 405
DS41391C-page 8
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1826/27
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Errata
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2010 Microchip Technology Inc.
Preliminary
DS41391C-page 9
PIC16F/LF1826/27
NOTES:
DS41391C-page 10
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1826/27
1.0 DEVICE OVERVIEW
The PIC16F/LF1826/27 are described within this data sheet. They are available in 18/20/28-pin packages. Figure 1-1 shows a block diagram of the PIC16F/LF1826/27 devices. Table 1-2 shows the pinout descriptions. Reference Table 1-1 for peripherals available per device.
TABLE 1-1:
DEVICE PERIPHERAL SUMMARY
PIC16F/LF1826 PIC16F/LF1827
Peripheral
ADC Capacitive Sensing Module Digital-to-Analog Converter (DAC) Digital Signal Modulator (DSM) EUSART Fixed Voltage Reference (FVR) Reference Clock Module SR Latch Capture/Compare/PWM Modules ECCP1 ECCP2 CCP3 CCP4 Comparators C1 C2 Master Synchronous Serial Ports MSSP1 MSSP2 Timers Timer0 Timer1 Timer2 Timer4 Timer6

2010 Microchip Technology Inc.
Preliminary
DS41391C-page 11
PIC16F/LF1826/27
FIGURE 1-1: PIC16F/LF1826/27 BLOCK DIAGRAM
Program Flash Memory CLKR RAM Clock Reference EEPROM
OSC2/CLKO OSC1/CLKI
Timing Generation INTRC Oscillator CPU (Figure 2-1) PORTB MCLR PORTA
SR Latch
ADC 10-Bit
Timer0
Timer1
Timer2Types
DAC
Comparators
ECCPx
CCPx
MSSPx
Modulator
EUSART
FVR
CapSense
Note
1: 2:
See applicable chapters for more information on peripherals. See Table 1-1 for peripherals available on specific devices.
DS41391C-page 12
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1826/27
TABLE 1-2: PIC16F/LF1826/27 PINOUT DESCRIPTION
Function RA0 AN0 CPS0 C12IN0SDO2 RA1/AN1/CPS1/C12IN1-/SS2(2) RA1 AN1 CPS1 C12IN1SS2 RA2/AN2/CPS2/C12IN2-/ C12IN+/VREF-/DACOUT RA2 AN2 CPS2 C12IN2C12IN+ VREFDACOUT RA3/AN3/CPS3/C12IN3-/C1IN+/ VREF+/C1OUT/CCP3(2)/SRQ RA3 AN3 CPS3 C12IN3C1IN+ VREF+ C1OUT CCP3 SRQ RA4/AN4/CPS4/C2OUT/T0CKI/ CCP4(2)/SRNQ RA4 AN4 CPS4 C2OUT T0CKI CCP4 SRNQ RA5/MCLR/VPP/SS1(1,2) RA5 MCLR VPP SS1 Input Type TTL AN AN AN -- TTL AN AN AN ST TTL AN AN AN AN AN -- TTL AN AN AN AN AN -- ST -- TTL AN AN -- ST ST -- TTL ST HV ST Output Type CMOS General purpose I/O. -- -- -- A/D Channel 0 input. Capacitive sensing input 0. Comparator C1 or C2 negative input. Description
Name RA0/AN0/CPS0/C12IN0-/ SDO2(2)
CMOS SPI data output. CMOS General purpose I/O. -- -- -- -- -- -- -- -- -- AN -- -- -- -- -- A/D Channel 1 input. Capacitive sensing input 1. Comparator C1 or C2 negative input. Slave Select input 2. A/D Channel 2 input. Capacitive sensing input 2. Comparator C1 or C2 negative input. Comparator C1 or C2 positive input. A/D Negative Voltage Reference input. Voltage Reference output. A/D Channel 3 input. Capacitive sensing input 3. Comparator C1 or C2 negative input. Comparator C1 positive input. A/D Voltage Reference input.
CMOS General purpose I/O.
CMOS General purpose I/O.
CMOS Comparator C1 output. CMOS Capture/Compare/PWM3. CMOS SR latch non-inverting output. CMOS General purpose I/O. -- -- -- A/D Channel 4 input. Capacitive sensing input 4. Timer0 clock input.
CMOS Comparator C2 output. CMOS Capture/Compare/PWM4. CMOS SR latch inverting output. CMOS General purpose I/O. -- -- -- Master Clear with internal pull-up. Programming voltage. Slave Select input 1.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Functions are only available on the PIC16F/LF1827. 3: Default function location.
2010 Microchip Technology Inc.
Preliminary
DS41391C-page 13
PIC16F/LF1826/27
TABLE 1-2: PIC16F/LF1826/27 PINOUT DESCRIPTION (CONTINUED)
Function RA6 OSC2 CLKOUT CLKR P1D P2B SDO1 RA7/OSC1/CLKIN/P1C(1)/ CCP2(1,2)/P2A(1,2) RA7 OSC1 CLKIN P1C CCP2 P2A RB0/T1G/CCP1 /P1A /INT/ SRI/FLT0
(1) (1)
Name RA6/OSC2/CLKOUT/CLKR/ P1D(1)/P2B(1,2)/SDO1(1)
Input Type TTL -- -- -- -- -- -- TTL XTAL CMOS -- ST -- TTL ST ST -- ST ST ST TTL AN AN ST ST I2CTM CMOS TTL AN AN -- -- ST ST ST I2CTM ST --
Output Type CMOS General purpose I/O. XTAL
Description
Crystal/Resonator (LP, XT, HS modes).
CMOS FOSC/4 output. CMOS Clock Reference Output. CMOS PWM output. CMOS PWM output. CMOS SPI data output 1. CMOS General purpose I/O. -- -- Crystal/Resonator (LP, XT, HS modes). External clock input (EC mode).
CMOS PWM output. CMOS Capture/Compare/PWM2. CMOS PWM output. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. -- Timer1 Gate input. CMOS Capture/Compare/PWM1. CMOS PWM output. -- -- -- External interrupt. SR latch input. ECCP Auto-Shutdown Fault input.
RB0 T1G CCP1 P1A INT SRI FLT0
RB1/AN11/CPS11/RX(1,3)/ DT(1,3)/SDA1/SDI1
RB1 AN11 CPS11 RX DT SDA1 SDI1
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. -- -- -- OD -- A/D Channel 11 input. Capacitive sensing input 11. USART asynchronous input. I2CTM data input/output 1. SPI data input 1.
CMOS USART synchronous data.
RB2/AN10/CPS10/MDMIN/ TX(1,3)/CK(1,3)/RX(1)/DT(1)/ SDA2(2)/SDI2(2)/SDO1(1,3)
RB2 AN10 CPS10 MDMIN TX CK RX DT SDA2 SDI2 SDO1
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. -- -- A/D Channel 10 input. Capacitive sensing input 10.
CMOS Modulator source input. CMOS USART asynchronous transmit. CMOS USART synchronous clock. -- OD -- USART asynchronous input. I2CTM data input/output 2. SPI data input 2. CMOS USART synchronous data.
CMOS SPI data output 1.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Functions are only available on the PIC16F/LF1827. 3: Default function location.
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Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1826/27
TABLE 1-2: PIC16F/LF1826/27 PINOUT DESCRIPTION (CONTINUED)
Function RB3 AN9 CPS9 MDOUT CCP1 P1A RB4/AN8/CPS8/SCL1/SCK1/ MDCIN2 RB4 AN8 CPS8 SCL1 SCK1 MDCIN2 RB5/AN7/CPS7/P1B/TX(1)/CK(1)/ SCL2(2)/SCK2(2)/SS1(1,3) RB5 AN7 CPS7 P1B TX CK SCL2 SCK2 SS1 RB6/AN5/CPS5/T1CKI/T1OSI/ P1C(1,3)/CCP2(1,2,3)/P2A(1,2,3)/ ICSPCLK RB6 AN5 CPS5 T1CKI T1OSO P1C CCP2 P2A ICSPCLK RB7/AN6/CPS6/T1OSO/ P1D(1,3)/P2B(1,2,3)/MDCIN1/ ICSPDAT RB7 AN6 CPS6 T1OSO P1D P2B MDCIN1 ICSPDAT Input Type TTL AN AN -- ST -- TTL AN AN I CTM ST ST TTL AN AN -- -- ST I2CTM ST ST TTL AN AN ST XTAL -- ST -- ST TTL AN AN XTAL -- -- ST ST
2
Name RB3/AN9/CPS9/MDOUT/ CCP1(1,3)/P1A(1,3)
Output Type
Description
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. -- -- A/D Channel 9 input. Capacitive sensing input 9.
CMOS Modulator output. CMOS Capture/Compare/PWM1. CMOS PWM output. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. -- -- OD -- A/D Channel 8 input. Capacitive sensing input 8. I2CTM clock 1. Modulator Carrier Input 2.
CMOS SPI clock 1. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. -- -- A/D Channel 7 input. Capacitive sensing input 7.
CMOS PWM output. CMOS USART asynchronous transmit. CMOS USART synchronous clock. OD -- I2CTM clock 2. Slave Select input 1. CMOS SPI clock 2. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. -- -- -- XTAL A/D Channel 5 input. Capacitive sensing input 5. Timer1 clock input. Timer1 oscillator connection.
CMOS PWM output. CMOS Capture/Compare/PWM2. CMOS PWM output. -- Serial Programming Clock. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. -- -- XTAL A/D Channel 6 input. Capacitive sensing input 6. Timer1 oscillator connection.
CMOS PWM output. CMOS PWM output. -- Modulator Carrier Input 1. CMOS ICSPTM Data I/O.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Functions are only available on the PIC16F/LF1827. 3: Default function location.
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Preliminary
DS41391C-page 15
PIC16F/LF1826/27
TABLE 1-2: PIC16F/LF1826/27 PINOUT DESCRIPTION (CONTINUED)
Function VDD VSS Input Type Power Power Output Type -- -- Positive supply. Ground reference. Description Name VDD VSS
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Functions are only available on the PIC16F/LF1827. 3: Default function location.
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Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1826/27
2.0 ENHANCED MID-RANGE CPU
This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, indirect, and relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. * * * * Automatic Interrupt Context Saving 16-level Stack with Overflow and Underflow File Select Registers Instruction Set
2.1
Automatic Interrupt Context Saving
During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 8.5 "Automatic Context Saving", for more information.
2.2
16-level Stack with Overflow and Underflow
These devices have an external stack memory 15 bits wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled will cause a software Reset. See section Section 3.4 "Stack" for more details.
2.3
File Select Registers
There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one data pointer for all memory. When an FSR points to program memory, there is 1 additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See Section 3.4 "Stack"for more details.
2.4
Instruction Set
There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 28.0 "Instruction Set Summary" for more details.
2010 Microchip Technology Inc.
Preliminary
DS41391C-page 17
PIC16F/LF1826/27
FIGURE 2-1: CORE BLOCK DIAGRAM
15
Configuration 15 Program Counter Flash Program Memory MUX Data Bus 8
16-LevelStack 8 Level Stack (15-bit) (13-bit) Program Memory Read (PMR) Direct Addr 7 5 BSR Reg FSR reg
RAM
Program Bus
14
12 Addr MUX
RAM Addr
Instruction Reg Instruction reg
Indirect Addr 12 12
15
FSR0 Reg FSR reg FSR1 reg FSR Reg 15 8 3 STATUS reg STATUS Reg
Power-up Timer Instruction Decode & Decode and Control Timing Generation Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset 8
MUX
ALU
OSC1/CLKIN OSC2/CLKOUT
W reg
Internal Oscillator Block VDD VSS
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Preliminary
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PIC16F/LF1826/27
3.0 MEMORY ORGANIZATION
There are three types of memory in PIC16F/LF1826/27: Data Memory, Program Memory and Data EEPROM Memory(1). * Program Memory * Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM - Device Memory Maps - Special Function Registers Summary * Data EEPROM memory(1) Note 1: The Data EEPROM Memory and the method to access Flash memory through the EECON registers is described in Section 11.0 "Data EEPROM and Flash Program Memory Control". The following features are associated with access and control of program memory and data memory: * PCL and PCLATH * Stack * Indirect Addressing
3.1
Program Memory Organization
The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program memory space. Table 3-1 shows the memory sizes implemented for the PIC16F/LF1826/27 family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figures 3-1 and 3-2).
TABLE 3-1:
DEVICE SIZES AND ADDRESSES
Device Program Memory Space (Words) 2,048 4,096 Last Program Memory Address 07FFh 0FFFh
PIC16F/LF1826 PIC16F/LF1827
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Preliminary
DS41391C-page 19
PIC16F/LF1826/27
FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16F/LF1826
PC<14:0> CALL, CALLW RETURN, RETLW Interrupt, RETFIE 15
FIGURE 3-2:
PROGRAM MEMORY MAP AND STACK FOR PIC16F/LF1827
PC<14:0>
CALL, CALLW RETURN, RETLW Interrupt, RETFIE
15
Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector Interrupt Vector On-chip Program Memory Page 0 Rollover to Page 0 Wraps to Page 0 07FFh 0800h 0000h 0004h 0005h On-chip Program Memory
Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector Interrupt Vector Page 0 07FFh 0800h Page 1 Rollover to Page 0 0FFFh 1000h 0000h 0004h 0005h
Wraps to Page 0
Wraps to Page 0
Rollover to Page 0
7FFFh
Rollover to Page 1
7FFFh
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Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1826/27
3.1.1 READING PROGRAM MEMORY AS DATA
There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory.
3.1.1.1
RETLW Instruction
The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1.
EXAMPLE 3-1:
constants brw
RETLW INSTRUCTION
;Add Index in W to ;program counter to ;select data ;Index0 data ;Index1 data
retlw retlw retlw retlw
DATA0 DATA1 DATA2 DATA3
my_function ;... LOTS OF CODE... movlw DATA_INDEX call constants ;... THE CONSTANT IS IN W
The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used.
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Preliminary
DS41391C-page 21
PIC16F/LF1826/27
3.1.1.2 Indirect Read with FSR 3.2.1 CORE REGISTERS
The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower 8 bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR. The HIGH directive will set bit<7> if a label points to a location in program memory. The core registers contain the registers that directly affect the basic operation of the PIC16F/LF1826/27. These registers are listed below: * * * * * * * * * * * * INDF0 INDF1 PCL STATUS FSR0 Low FSR0 High FSR1 Low FSR1 High BSR WREG PCLATH INTCON Note: The core registers are the first 12 addresses of every data memory bank.
EXAMPLE 3-2:
ACCESSING PROGRAM MEMORY VIA FSR
constants RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3 my_function ;... LOTS OF CODE... MOVLW LOW constants MOVWF FSR1L MOVLW HIGH constants MOVWF FSR1H MOVIW 0[FSR1] ;THE PROGRAM MEMORY IS IN W
3.2
Data Memory Organization
The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-3): * * * * 12 core registers 20 Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) 16 bytes of common RAM
The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as `0'. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section 3.5 "Indirect Addressing" for more information.
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Preliminary
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PIC16F/LF1826/27
3.2.1.1 STATUS Register
The STATUS register, shown in Register 3-1, contains: * the arithmetic status of the ALU * the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as `000u u1uu' (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to Section 28.0 "Instruction Set Summary"). Note 1: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction.
REGISTER 3-1:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-5 bit 4
STATUS: STATUS REGISTER
U-0 -- U-0 -- R-1/q TO R-1/q PD R/W-0/u Z R/W-0/u DC(1) R/W-0/u C(1) bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition
Unimplemented: Read as `0' TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit Carry/Digit Borrow bit(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result C: Carry/Borrow bit(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred For Borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.
bit 3
bit 2
bit 1
bit 0
Note 1:
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Preliminary
DS41391C-page 23
PIC16F/LF1826/27
3.2.2 SPECIAL FUNCTION REGISTER 3.2.5 DEVICE MEMORY MAPS
The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. The memory maps for the device family are as shown in Table 3-2.
TABLE 3-2:
Device
MEMORY MAP TABLES
Banks 0-7 8-15 16-23 24-31 31 Table No. Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 3-7
3.2.3
GENERAL PURPOSE RAM
PIC16F/LF1826/27
There are up to 80 bytes of GPR in each data memory bank.
3.2.3.1
Linear Access to GPR
The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See Section 3.5.2 "Linear Data Memory" for more information.
3.2.4
COMMON RAM
There are 16 bytes of common RAM accessible from all banks.
FIGURE 3-3:
BANKED MEMORY PARTITIONING
Memory Region
7-bit Bank Offset 00h
0Bh 0Ch
Core Registers (12 bytes)
Special Function Registers (20 bytes maximum) 1Fh 20h
General Purpose RAM (80 bytes maximum)
6Fh 70h Common RAM (16 bytes) 7Fh
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Preliminary
2010 Microchip Technology Inc.
TABLE 3-3:
BANK0
000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON PORTA PORTB -- -- -- PIR1 PIR2 PIR3(1) PIR4(1) TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON -- CPSCON0 CPSCON1
PIC16F/LF1826/27 MEMORY MAP, BANKS 0-7
BANK1
080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh 0A0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON TRISA TRISB -- -- -- PIE1 PIE2 PIE3(1) PIE4(1) OPTION PCON WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 -- General Purpose Register 80 Bytes 0EFh 0F0h Accesses 70h - 7Fh 16Fh 170h Accesses 70h - 7Fh 17Fh 1FFh 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h
2010 Microchip Technology Inc.
BANK2
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON LATA LATB -- -- -- CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON FVRCON DACCON0 DACCON1 SRCON0 SRCON1 -- APFCON0 APFCON1 -- General Purpose Register 80 Bytes 1EFh 1F0h 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h
BANK3
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON ANSELA ANSELB -- -- -- EEADRL EEADRH EEDATL EEDATH EECON1 EECON2 -- -- RCREG TXREG SPBRGL SPBRGH RCSTA TXSTA BAUDCON General Purpose Register 80 Bytes(1) 26Fh 270h Accesses 70h - 7Fh 27Fh 200h 201h 202h 203h 204h 205h 206h 207h 208h 209h 20Ah 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh 21Fh 220h
BANK4
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON WPUA WPUB -- -- -- SSP1BUF SSP1ADD SSP1MASK SSP1STAT SSP1CON SSP1CON2 SSP1CON3 -- SSP2BUF(1) SSP2ADD(1) SSP2MASK(1) SSP2STAT(1) SSP2CON(1) SSP2CON2(1) SSP2CON3(1) General Purpose Register 48 Bytes(1) Unimplemented Read as `0' Accesses 70h - 7Fh 2FFh 280h 281h 282h 283h 284h 285h 286h 287h 288h 289h 28Ah 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh 29Fh 2A0h
BANK5
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- CCPR1L CCPR1H CCP1CON PWM1CON CCP1AS PSTR1CON -- CCPR2L(1) CCPR2H(1) CCP2CON(1) PWM2CON(1) CCP2AS(1) PSTR2CON(1) CCPTMRS(1) -- 300h 301h 302h 303h 304h 305h 306h 307h 308h 309h 30Ah 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh 31Fh 320h
BANK6
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- CCPR3L(1) CCPR3H(1) CCP3CON(1) -- -- -- -- CCPR4L(1) CCPR4H(1) CCP4CON(1) -- -- -- -- -- 380h 381h 382h 383h 384h 385h 386h 387h 388h 389h 38Ah 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh 39Fh 3A0h
BANK7
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- IOCBP IOCBN IOCBF -- -- -- CLKRCON -- MDCON MDSRC MDCARL MDCARH
Preliminary
DS41391C-page 25
PIC16F/LF1826/27
06Fh 070h
General Purpose Register 96 Bytes
Unimplemented Read as `0' 2EFh 2F0h Accesses 70h - 7Fh 37Fh 36Fh 370h
Unimplemented Read as `0' 3EFh 3F0h Accesses 70h - 7Fh 3FFh
Unimplemented Read as `0'
Accesses 70h - 7Fh
07Fh Legend: Note 1:
0FFh
= Unimplemented data memory locations, read as `0' Available only on PIC16F/LF1827.
TABLE 3-4:
BANK 8
400h 401h 402h 403h 404h 405h 406h 407h 408h 409h 40Ah 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- TMR4(1) PR4(1) T4CON(1) -- -- -- -- TMR6(1) PR6(1) T6CON(1) --
PIC16F/LF1826/27 MEMORY MAP, BANKS 8-15
BANK 9
480h 481h 482h 483h 484h 485h 486h 487h 488h 489h 48Ah 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 500h 501h 502h 503h 504h 505h 506h 507h 508h 509h 50Ah 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 514h 515h 516h 517h 518h 519h 51Ah 51Bh 51Ch 51Dh 51Eh 51Fh 520h
DS41391C-page 26
PIC16F/LF1826/27
BANK 10
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 580h 581h 582h 583h 584h 585h 586h 587h 588h 589h 58Ah 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h 596h 597h 598h 599h 59Ah 59Bh 59Ch 59Dh 59Eh 59Fh 5A0h
BANK 11
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 600h 601h 602h 603h 604h 605h 606h 607h 608h 609h 60Ah 60Bh 60Ch 60Dh 60Eh 60Fh 610h 611h 612h 613h 614h 615h 616h 617h 618h 619h 61Ah 61Bh 61Ch 61Dh 61Eh 61Fh 620h
BANK 12
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 680h 681h 682h 683h 684h 685h 686h 687h 688h 689h 68Ah 68Bh 68Ch 68Dh 68Eh 68Fh 690h 691h 692h 693h 694h 695h 696h 697h 698h 699h 69Ah 69Bh 69Ch 69Dh 69Eh 69Fh 6A0h
BANK 13
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 700h 701h 702h 703h 704h 705h 706h 707h 708h 709h 70Ah 70Bh 70Ch 70Dh 70Eh 70Fh 710h 711h 712h 713h 714h 715h 716h 717h 718h 719h 71Ah 71Bh 71Ch 71Dh 71Eh 71Fh 720h
BANK 14
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 780h 781h 782h 783h 784h 785h 786h 787h 788h 789h 78Ah 78Bh 78Ch 78Dh 78Eh 78Fh 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah 79Bh 79Ch 79Dh 79Eh 79Fh 7A0h
BANK 15
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Preliminary
2010 Microchip Technology Inc.
Unimplemented Read as `0' 46Fh 470h Accesses 70h - 7Fh 47Fh Legend: 4FFh 4EFh 4F0h
Unimplemented Read as `0' 56Fh 570h Accesses 70h - 7Fh 57Fh
Unimplemented Read as `0' 5EFh 5F0h Accesses 70h - 7Fh 5FFh
Unimplemented Read as `0' 66Fh 670h Accesses 70h - 7Fh 67Fh
Unimplemented Read as `0' 6EFh 6F0h Accesses 70h - 7Fh 6FFh
Unimplemented Read as `0' 76Fh 770h Accesses 70h - 7Fh 77Fh
Unimplemented Read as `0' 7EFh 7F0h Accesses 70h - 7Fh 7FFh
Unimplemented Read as `0'
Accesses 70h - 7Fh
= Unimplemented data memory locations, read as `0'
TABLE 3-5:
BANK16
800h 801h 802h 803h 804h 805h 806h 807h 808h 809h 80Ah 80Bh 80Ch 80Dh 80Eh 80Fh 810h 811h 812h 813h 814h 815h 816h 817h 818h 819h 81Ah 81Bh 81Ch 81Dh 81Eh 81Fh 820h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
PIC16F/LF1826/27 MEMORY MAP, BANKS 16-23)
BANK17
880h 881h 882h 883h 884h 885h 886h 887h 888h 889h 88Ah 88Bh 88Ch 88Dh 88Eh 88Fh 890h 891h 892h 893h 894h 895h 896h 897h 898h 899h 89Ah 89Bh 89Ch 89Dh 89Eh 89Fh 8A0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 900h 901h 902h 903h 904h 905h 906h 907h 908h 909h 90Ah 90Bh 90Ch 90Dh 90Eh 90Fh 910h 911h 912h 913h 914h 915h 916h 917h 918h 919h 91Ah 91Bh 91Ch 91Dh 91Eh 91Fh 920h
2010 Microchip Technology Inc.
BANK18
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 980h 981h 982h 983h 984h 985h 986h 987h 988h 989h 98Ah 98Bh 98Ch 98Dh 98Eh 98Fh 990h 991h 992h 993h 994h 995h 996h 997h 998h 999h 99Ah 99Bh 99Ch 99Dh 99Eh 99Fh 9A0h
BANK19
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- A00h A01h A02h A03h A04h A05h A06h A07h A08h A09h A0Ah A0Bh A0Ch A0Dh A0Eh A0Fh A10h A11h A12h A13h A14h A15h A16h A17h A18h A19h A1Ah A1Bh A1Ch A1Dh A1Eh A1Fh A20h
BANK20
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- A80h A81h A82h A83h A84h A85h A86h A87h A88h A89h A8Ah A8Bh A8Ch A8Dh A8Eh A8Fh A90h A91h A92h A93h A94h A95h A96h A97h A98h A99h A9Ah A9Bh A9Ch A9Dh A9Eh A9Fh AA0h
BANK21
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B00h B01h B02h B03h B04h B05h B06h B07h B08h B09h B0Ah B0Bh B0Ch B0Dh B0Eh B0Fh B10h B11h B12h B13h B14h B15h B16h B17h B18h B19h B1Ah B1Bh B1Ch B1Dh B1Eh B1Fh B20h
BANK22
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B80h B81h B82h B83h B84h B85h B86h B87h B88h B89h B8Ah B8Bh B8Ch B8Dh B8Eh B8Fh B90h B91h B92h B93h B94h B95h B96h B97h B98h B99h B9Ah B9Bh B9Ch B9Dh B9Eh B9Fh BA0h
BANK23
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Preliminary
DS41391C-page 27
PIC16F/LF1826/27
Unimplemented Read as `0' 86Fh 870h Accesses 70h - 7Fh 87Fh Legend: 8FFh 8EFh 8F0h
Unimplemented Read as `0' 96Fh 970h Accesses 70h - 7Fh 97Fh
Unimplemented Read as `0' 9EFh 9F0h Accesses 70h - 7Fh 9FFh
Unimplemented Read as `0' A6Fh A70h Accesses 70h - 7Fh A7Fh
Unimplemented Read as `0' AEFh AF0h Accesses 70h - 7Fh AFFh
Unimplemented Read as `0' B6Fh B70h Accesses 70h - 7Fh B7Fh
Unimplemented Read as `0' BEFh BF0h Accesses 70h - 7Fh BFFh
Unimplemented Read as `0'
Accesses 70h - 7Fh
= Unimplemented data memory locations, read as `0'
TABLE 3-6:
C00h C01h C02h C03h C04h C05h C06h C07h C08h C09h C0Ah C0Bh C0Ch C0Dh C0Eh C0Fh C10h C11h C12h C13h C14h C15h C16h C17h C18h C19h C1Ah C1Bh C1Ch C1Dh C1Eh C1Fh C20h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
PIC16F/LF1826/27 MEMORY MAP, BANKS 24-31
BANK 25
C80h C81h C82h C83h C84h C85h C86h C87h C88h C89h C8Ah C8Bh C8Ch C8Dh C8Eh C8Fh C90h C91h C92h C93h C94h C95h C96h C97h C98h C99h C9Ah C9Bh C9Ch C9Dh C9Eh C9Fh CA0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- D00h D01h D02h D03h D04h D05h D06h D07h D08h D09h D0Ah D0Bh D0Ch D0Dh D0Eh D0Fh D10h D11h D12h D13h D14h D15h D16h D17h D18h D19h D1Ah D1Bh D1Ch D1Dh D1Eh D1Fh D20h
DS41391C-page 28
PIC16F/LF1826/27
BANK 24
BANK 26
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- D80h D81h D82h D83h D84h D85h D86h D87h D88h D89h D8Ah D8Bh D8Ch D8Dh D8Eh D8Fh D90h D91h D92h D93h D94h D95h D96h D97h D98h D99h D9Ah D9Bh D9Ch D9Dh D9Eh D9Fh DA0h
BANK 27
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- E00h E01h E02h E03h E04h E05h E06h E07h E08h E09h E0Ah E0Bh E0Ch E0Dh E0Eh E0Fh E10h E11h E12h E13h E14h E15h E16h E17h E18h E19h E1Ah E1Bh E1Ch E1Dh E1Eh E1Fh E20h
BANK 28
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- E80h E81h E82h E83h E84h E85h E86h E87h E88h E89h E8Ah E8Bh E8Ch E8Dh E8Eh E8Fh E90h E91h E92h E93h E94h E95h E96h E97h E98h E99h E9Ah E9Bh E9Ch E9Dh E9Eh E9Fh EA0h
BANK 29
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- F00h F01h F02h F03h F04h F05h F06h F07h F08h F09h F0Ah F0Bh F0Ch F0Dh F0Eh F0Fh F10h F11h F12h F13h F14h F15h F16h F17h F18h F19h F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h
BANK 30
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- F80h F81h F82h F83h F84h F85h F86h F87h F88h F89h F8Ah F8Bh F8Ch F8Dh F8Eh F8Fh F90h F91h F92h F93h F94h F95h F96h F97h F98h F99h F9Ah F9Bh F9Ch F9Dh F9Eh F9Fh FA0h
BANK 31
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Preliminary
2010 Microchip Technology Inc.
Unimplemented Read as `0' C6Fh C70h Accesses 70h - 7Fh CFFh Legend: CFFh CEFh CF0h
Unimplemented Read as `0' D6Fh D70h Accesses 70h - 7Fh D7Fh
Unimplemented Read as `0' DEFh DF0h Accesses 70h - 7Fh DFFh
Unimplemented Read as `0' E6Fh E70h Accesses 70h - 7Fh E7Fh
Unimplemented Read as `0' EEFh EF0h Accesses 70h - 7Fh EFFh
Unimplemented Read as `0' F6Fh F70h Accesses 70h - 7Fh F7Fh
Unimplemented Read as `0' FEFh FF0h Accesses 70h - 7Fh FFFh
See Table 3-7 for more information
Accesses 70h - 7Fh
= Unimplemented data memory locations, read as `0'
PIC16F/LF1826/27
TABLE 3-7: PIC16F/LF1826/27 MEMORY MAP, BANK 31
Bank 31
FA0h Unimplemented Read as `0' FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh Legend:
3.2.6
SPECIAL FUNCTION REGISTERS SUMMARY
The Special Function Register Summary for the device family are as follows: Device Bank(s) 0 1 2 3 4 PIC16F/LF1826/27 5 6 7 8 9-30 31 Page No. 30 31 32 33 34 35 36 37 38 39 40
STATUS_SHAD WREG_SHAD BSR_SHAD PCLATH_SHAD FSR0L_SHAD FSR0H_SHAD FSR1L_SHAD FSR1H_SHAD -- STKPTR TOSL TOSH = Unimplemented data memory locations, read as `0'.
2010 Microchip Technology Inc.
Preliminary
DS41391C-page 29
PIC16F/LF1826/27
TABLE 3-8:
Address Bank 0 000h(2) 001h(2) 002h(2) 003h(2) 004h(2) 005h(2) 006h(2) 007h(2) 008h(2) 009h(2) 00Ah(2) 00Bh(2) 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh Legend: Note 1: 2: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON PORTA PORTB -- -- -- PIR1 PIR2 PIR3(1) PIR4(1) TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON -- CPSCON0 CPSCON1 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- Working Register -- GIE RA7 RB7 Unimplemented Unimplemented Unimplemented TMR1GIF OSFIF -- -- ADIF C2IF -- -- RCIF C1IF CCP4IF -- TXIF EEIF CCP3IF -- SSP1IF BCL1IF TMR6IF -- CCP1IF -- -- -- TMR2IF -- TMR4IF BCL2IF TMR1IF -- SSP2IF Write Buffer for the upper 7 bits of the Program Counter PEIE RA6 RB6 TMR0IE RA5 RB5 INTE RA4 RB4 IOCIE RA3 RB3 TMR0IF RA2 RB2 INTF RA1 RB1 IOCIF RA0 RB0 -- -- BSR4 BSR3 BSR2 BSR1 BSR0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 0000 000x 0000 000u xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -- -- -- -- -- -- Name
SPECIAL FUNCTION REGISTER SUMMARY
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets
0000 0000 0000 0000 --00 0-0- --00 0-0---- --00 ---- --00 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
CCP2IF(1) 0000 0--0 0000 0--0
Timer0 Module Register Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TMR1CS1 TMR1GE TMR1CS0 T1GPOL T1CKPS1 T1GTM T1CKPS0 T1GSPM T1OSCEN T1GGO/ DONE T1SYNC T1GVAL -- T1GSS1 TMR1ON T1GSS0
0000 00-0 uuuu uu-u 0000 0x00 uuuu uxuu 0000 0000 0000 0000 1111 1111 1111 1111
Timer2 Module Register Timer2 Period Register -- CPSON -- T2OUTPS3 -- -- T2OUTPS2 -- -- T2OUTPS1 T2OUTPS0 -- -- TMR2ON Unimplemented CPSRNG1 CPSRNG0 CPSOUT CPSCH3 CPSCH2 CPSCH1 T0XCS CPSCH0
T2CKPS1 T2CKPS0 -000 0000 -000 0000 -- -- 0--- 0000 0--- 0000 ---- 0000 ---- 0000
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F/LF1827 only. These registers can be addressed from any bank.
DS41391C-page 30
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1826/27
TABLE 3-8:
Address Bank 1 080h(2) 081h(2) 082h(2) 083h(2) 084h(2) 085h(2) 086h(2) 087h(2) 088h(2) 089h(2) 08Ah(2) 08Bh(2) 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh Legend: Note 1: 2: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON TRISA TRISB -- -- -- PIE1 PIE2 PIE3
(1)
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets
Name
Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- Working Register -- GIE TRISA7 TRISB7 Unimplemented Unimplemented Unimplemented TMR1GIE OSFIE -- -- WPUEN STKOVF -- -- SPLLEN T1OSCR ADIE C2IE -- -- INTEDG STKUNF -- -- IRCF3 PLLR RCIE C1IE CCP4IE -- TMR0CS -- WDTPS4 TUN5 IRCF2 OSTS TXIE EEIE CCP3IE -- TMR0SE -- WDTPS3 TUN4 IRCF1 HFIOFR SSP1IE BCL1IE TMR6IE -- PSA RMCLR WDTPS2 TUN3 IRCF0 HFIOFL CCP1IE -- -- -- PS2 RI WDTPS1 TUN2 -- MFIOFR TMR2IE -- TMR4IE BCL2IE PS1 POR WDTPS0 TUN1 SCS1 LFIOFR TMR1IE -- SSP2IE PS0 BOR TUN0 SCS0 HFIOFS Write Buffer for the upper 7 bits of the Program Counter PEIE TRISA6 TRISB6 TMR0IE TRISA5 TRISB5 INTE TRISA4 TRISB4 IOCIE TRISA3 TRISB3 TMR0IF TRISA2 TRISB2 INTF TRISA1 TRISB1 IOCIF TRISA0 TRISB0 -- -- BSR4 BSR3 BSR2 BSR1 BSR0
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 0000 000x 0000 000u 1111 1111 1111 1111 1111 1111 1111 1111 -- -- -- -- -- --
0000 0000 0000 0000 --00 0-0- --00 0-0---- --00 ---- --00 1111 1111 1111 1111 00-- 11qq qq-- qquu --00 0000 --00 0000 0011 1-00 0011 1-00 10q0 0q00 qqqq qq0q xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
CCP2IE(1) 0000 0--0 0000 0--0
PIE4(1) OPTION_REG PCON WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 --
SWDTEN --01 0110 --01 0110
A/D Result Register Low A/D Result Register High -- ADFM Unimplemented CHS4 ADCS2 CHS3 ADCS1 CHS2 ADCS0 CHS1 -- CHS0 ADNREF GO/DONE ADPREF1 ADON
-000 0000 -000 0000 -- --
ADPREF0 0000 -000 0000 -000
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F/LF1827 only. These registers can be addressed from any bank.
2010 Microchip Technology Inc.
Preliminary
DS41391C-page 31
PIC16F/LF1826/27
TABLE 3-8:
Address Bank 2 100h(2) 101h(2) 102h(2) 103h(2) 104h(2) 105h(2) 106h(2) 107h(2) 108h(2) 109h(2) 10Ah(2) 10Bh(2) 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh Legend: Note 1: 2: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON LATA LATB -- -- -- CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON FVRCON DACCON0 DACCON1 SRCON0 SRCON1 -- APFCON0 APFCON1 -- Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- Working Register -- GIE LATA7 LATB7 Unimplemented Unimplemented Unimplemented C1ON C1INTP C2ON C2INTP -- SBOREN FVREN DACEN -- SRLEN SRSPE RXDTSEL -- Unimplemented Unimplemented SDO1SEL -- SS1SEL -- P2BSEL(1) CCP2SEL(1) -- -- P1DSEL -- P1CSEL -- C1OUT C1INTN C2OUT C2INTN -- -- FVRRDY DACLPS -- SRCLK2 SRSCKE C1OE C1PCH1 C2OE C2PCH1 -- -- Reserved DACOE -- SRCLK1 SRSC2E C1POL C1PCH0 C2POL C2PCH0 -- -- Reserved -- DACR4 SRCLK0 SRSC1E -- -- -- -- -- -- CDAFVR1 DACPSS1 DACR3 SRQEN SRRPE C1SP -- C2SP -- -- -- CDAFVR0 DACPSS0 DACR2 SRNQEN SRRCKE C1HYS C1NCH1 C2HYS C2NCH1 MC2OUT -- ADFVR1 -- DACR1 SRPS SRRC2E C1SYNC C1NCH0 C2SYNC C2NCH0 MC1OUT ADFVR0 DACNSS DACR0 SRPR SRRC1E Write Buffer for the upper 7 bits of the Program Counter PEIE LATA6 LATB6 TMR0IE -- LATB5 INTE LATA4 LATB4 IOCIE LATA3 LATB3 TMR0IF LATA2 LATB2 INTF LATA1 LATB1 IOCIF LATA0 LATB0 -- -- BSR4 BSR3 BSR2 BSR1 BSR0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 0000 000x 0000 000u xx-x xxxx uu-u uuuu xxxx xxxx uuuu uuuu -- -- -- -- -- -- Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets
0000 -100 0000 -100 0000 --00 0000 --00 0000 -100 0000 -100 0000 --00 0000 --00 ---- --00 ---- --00 0qrr 0000 0qrr 0000 000- 00-0 000- 00-0 ---0 0000 ---0 0000 0000 0000 0000 0000 0000 0000 0000 0000 -- --
BORRDY 1--- ---q u--- ---u
CCP1SEL 0000 0000 0000 0000 TXCKSEL ---- ---0 ---- ---0 -- --
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F/LF1827 only. These registers can be addressed from any bank.
DS41391C-page 32
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1826/27
TABLE 3-8:
Address Bank 3 180h(2) 181h(2) 182h(2) 183h(2) 184h(2) 185h(2) 186h(2) 187h(2) 188h(2) 189h(2) 18Ah(2) 18Bh(2) 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh Legend: Note 1: 2: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON ANSELA ANSELB -- -- -- EEADRL EEADRH EEDATL EEDATH EECON1 EECON2 -- -- RCREG TXREG SPBRGL SPBRGH RCSTA TXSTA BAUDCON Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- Working Register -- GIE -- ANSB7 Unimplemented Unimplemented Unimplemented EEPROM / Program Memory Address Register Low Byte -- -- EEPGD Unimplemented Unimplemented USART Receive Data Register USART Transmit Data Register Baud Rate Generator Data Register Low Baud Rate Generator Data Register High SPEN CSRC ABDOVF RX9 TX9 RCIDL SREN TXEN -- CREN SYNC SCKP ADDEN SENDB BRG16 FERR BRGH -- OERR TRMT WUE RX9D TX9D ABDEN EEPROM / Program Memory Address Register High Byte -- CFGS EEPROM / Program Memory Read Data Register High Byte LWLO FREE WRERR WREN WR RD EEPROM / Program Memory Read Data Register Low Byte Write Buffer for the upper 7 bits of the Program Counter PEIE -- ANSB6 TMR0IE -- ANSB5 INTE ANSA4 ANSB4 IOCIE ANSA3 ANSB3 TMR0IF ANSA2 ANSB2 INTF ANSA1 ANSB1 IOCIF ANSA0 -- -- -- BSR4 BSR3 BSR2 BSR1 BSR0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 0000 000x 0000 000u ---1 1111 ---1 1111 1111 111- 1111 111-- -- -- -- -- -- Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets
0000 0000 0000 0000 -000 0000 -000 0000 xxxx xxxx uuuu uuuu --xx xxxx --uu uuuu 0000 x000 0000 q000 0000 0000 0000 0000 -- -- -- --
EEPROM control register 2
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 000x 0000 000x 0000 0010 0000 0010 01-0 0-00 01-0 0-00
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F/LF1827 only. These registers can be addressed from any bank.
2010 Microchip Technology Inc.
Preliminary
DS41391C-page 33
PIC16F/LF1826/27
TABLE 3-8:
Address Bank 4 200h(2) 201h(2) 202h(2) 203h(2) 204h(2) 205h(2) 206h(2) 207h(2) 208h(2) 209h(2) 20Ah(2) 20Bh(2) 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh 21Fh Legend: Note 1: 2: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON WPUA WPUB -- -- -- SSP1BUF SSP1ADD SSP1MSK SSP1STAT SSP1CON1 SSP1CON2 SSP1CON3 -- SSP2BUF(1) SSP2ADD(1) SSP2MSK(1) SSP2STAT(1) SSP2CON1(1) SSP2CON2(1) SSP2CON3(1) Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- Working Register -- GIE -- WPUB7 Unimplemented Unimplemented Unimplemented Synchronous Serial Port Receive Buffer/Transmit Register ADD7 MSK7 SMP WCOL GCEN ACKTIM Unimplemented Synchronous Serial Port Receive Buffer/Transmit Register ADD7 MSK7 SMP WCOL GCEN ACKTIM ADD6 MSK6 CKE SSPOV ACKSTAT PCIE ADD5 MSK5 D/A SSPEN ACKDT SCIE ADD4 MSK4 P CKP ACKEN BOEN ADD3 MSK3 S SSPM3 RCEN SDAHT ADD2 MSK2 R/W SSPM2 PEN SBCDE ADD1 MSK1 UA SSPM1 RSEN AHEN ADD0 MSK0 BF SSPM0 SEN DHEN ADD6 MSK6 CKE SSPOV ACKSTAT PCIE ADD5 MSK5 D/A SSPEN ACKDT SCIE ADD4 MSK4 P CKP ACKEN BOEN ADD3 MSK3 S SSPM3 RCEN SDAHT ADD2 MSK2 R/W SSPM2 PEN SBCDE ADD1 MSK1 UA SSPM1 RSEN AHEN ADD0 MSK0 BF SSPM0 SEN DHEN Write Buffer for the upper 7 bits of the Program Counter PEIE -- WPUB6 TMR0IE WPUA5 WPUB5 INTE -- WPUB4 IOCIE -- WPUB3 TMR0IF -- WPUB2 INTF -- WPUB1 IOCIF -- WPUB0 -- -- BSR4 BSR3 BSR2 BSR1 BSR0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 0000 000x 0000 000u --1- ---- --1- ---1111 1111 1111 1111 -- -- -- -- -- -- Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets
xxxx xxxx uuuu uuuu 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -- -- xxxx xxxx uuuu uuuu 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F/LF1827 only. These registers can be addressed from any bank.
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TABLE 3-8:
Address Bank 5 280h(2) 281h(2) 282h(2) 283h(2) 284h(2) 285h(2) 286h(2) 287h(2) 288h(2) 289h(2) 28Ah(2) 28Bh(2) 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh 29Fh Legend: Note 1: 2: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- CCPR1L CCPR1H CCP1CON PWM1CON CCP1AS PSTR1CON -- CCPR2L(1) CCPR2H(1) CCP2CON(1) PWM2CON(1) CCP2AS(1) PSTR2CON(1) CCPTMRS(1) -- Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- Working Register -- GIE Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Capture/Compare/PWM Register 1 (LSB) Capture/Compare/PWM Register 1 (MSB) P1M1 P1RSEN CCP1ASE -- Unimplemented Capture/Compare/PWM Register 2 (LSB) Capture/Compare/PWM Register 2 (MSB) P2M1 P2RSEN CCP2ASE -- C4TSEL1 Unimplemented P2M0 P2DC6 CCP2AS2 -- C4TSEL0 DC2B1 P2DC5 CCP2AS1 -- C3TSEL1 DC2B0 P2DC4 CCP2AS0 STR2SYNC C3TSEL0 CCP2M3 P2DC3 PSS2AC1 STR2D C2TSEL1 CCP2M2 P2DC2 STR2C C2TSEL0 CCP2M1 P2DC1 STR2B C1TSEL1 CCP2M0 P2DC0 STR2A P1M0 P1DC6 CCP1AS2 -- DC1B1 P1DC5 CCP1AS1 -- DC1B0 P1DC4 CCP1AS0 STR1SYNC CCP1M3 P1DC3 PSS1AC1 STR1D CCP1M2 P1DC2 STR1C CCP1M1 P1DC1 STR1B CCP1M0 P1DC0 STR1A Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF -- -- BSR4 BSR3 BSR2 BSR1 BSR0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 0000 000x 0000 000u -- -- -- -- -- -- -- -- -- -- Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 ---0 0001 ---0 0001 -- -- xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 ---0 0001 ---0 0001 -- --
PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 0000 0000
PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 0000 0000 C1TSEL0 0000 0000 0000 0000
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F/LF1827 only. These registers can be addressed from any bank.
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TABLE 3-8:
Address Bank 6 300h(2) 301h(2) 302h(2) 303h(2) 304h(2) 305h(2) 306h(2) 307h(2) 308h(2) 309h(2) 30Ah(2) 30Bh(2) 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh 31Fh Legend: Note 1: 2: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- CCPR3L(1) CCPR3H(1) CCP3CON(1) -- -- -- -- CCPR4L(1) CCPR4H(1) CCP4CON(1) -- -- -- -- -- Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- Working Register -- GIE Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Capture/Compare/PWM Register 3 (LSB) Capture/Compare/PWM Register 3 (MSB) -- Unimplemented Unimplemented Unimplemented Unimplemented Capture/Compare/PWM Register 4 (LSB) Capture/Compare/PWM Register 4 (MSB) -- Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented -- DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 -- DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF -- -- BSR4 BSR3 BSR2 BSR1 BSR0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 0000 000x 0000 000u -- -- -- -- -- -- -- -- -- -- Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --00 0000 --00 0000 -- -- -- -- -- -- -- --
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --00 0000 --00 0000 -- -- -- -- -- -- -- -- -- --
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F/LF1827 only. These registers can be addressed from any bank.
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TABLE 3-8:
Address Bank 7 380h(2) 381h(2) 382h(2) 383h(2) 384h(2) 385h(2) 386h(2) 387h(2) 388h(2) 389h(2) 38Ah(2) 38Bh(2) 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh 39Fh Legend: Note 1: 2: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- IOCBP IOCBN IOCBF -- -- -- CLKRCON -- MDCON MDSRC MDCARL MDCARH Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- Working Register -- GIE Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented IOCBP7 IOCBN7 IOCBF7 Unimplemented Unimplemented Unimplemented CLKREN MDEN MDMSODIS MDCLODIS MDCHODIS CLKROE MDOE -- MDCLPOL CLKRSLR MDSLR -- MDCLSYNC CLKRDC1 MDOPOL -- -- -- CLKRDC0 -- MDMS3 MDCL3 MDCH3 Unimplemented -- MDMS2 MDCL2 MDCH2 -- MDMS1 MDCL1 MDCH1 MDBIT MDMS0 MDCL0 MDCH0 IOCBP6 IOCBN6 IOCBF6 IOCBP5 IOCBN5 IOCBF5 IOCBP4 IOCBN4 IOCBF4 IOCBP3 IOCBN3 IOCBF3 IOCBP2 IOCBN2 IOCBF2 IOCBP1 IOCBN1 IOCBF1 IOCBP0 IOCBN0 IOCBF0 Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF -- -- BSR4 BSR3 BSR2 BSR1 BSR0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 0000 000x 0000 000u -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -- -- -- -- -- -- -- --
CLKRDIV2 CLKRDIV1 CLKRDIV0 0011 0000 0011 0000 0010 ---0 0010 ---0 x--- xxxx u--- uuuu xxx- xxxx uuu- uuuu xxx- xxxx uuu- uuuu
MDCHPOL MDCHSYNC
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F/LF1827 only. These registers can be addressed from any bank.
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TABLE 3-8:
Address Bank 8 400h(2) 401h(2) 402h(2) 403h(2) 404h(2) 405h(2) 406h(2) 407h(2) 408h(2) 409h(2) 40Ah(2) 40Bh(2) 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh Legend: Note 1: 2: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- TMR4(1) PR4(1) T4CON(1) -- -- -- -- TMR6(1) PR6(1) T6CON(1) -- Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- Working Register -- GIE Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Timer4 Module Register Timer4 Period Register -- T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON Unimplemented Unimplemented Unimplemented Unimplemented Timer6 Module Register Timer6 Period Register -- T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 TMR6ON Unimplemented Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF -- -- BSR4 BSR3 BSR2 BSR1 BSR0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 0000 000x 0000 000u -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets
0000 0000 0000 0000 1111 1111 1111 1111 T4CKPS1 T4CKPS0 -000 0000 -000 0000 -- -- -- -- -- -- -- --
0000 0000 0000 0000 1111 1111 1111 1111 T6CKPS1 T6CKPS0 -000 0000 -000 0000 -- --
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F/LF1827 only. These registers can be addressed from any bank.
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TABLE 3-8:
Address Banks 9-30 x00h/ x80h(2) x00h/ x81h(2) x02h/ x82h(2) x03h/ x83h(2) x04h/ x84h(2) x05h/ x85h(2) x06h/ x86h(2) x07h/ x87h(2) x08h/ x88h(2) x09h/ x89h(2) x0Ah/ x8Ah(2) x0Bh/ x8Bh(2) x0Ch/ x8Ch -- x1Fh/ x9Fh Legend: Note 1: 2: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 TMR0IF INTF IOCIF 0000 000x 0000 000u -- -- Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets
Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- Working Register -- GIE Unimplemented Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE -- --
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F/LF1827 only. These registers can be addressed from any bank.
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TABLE 3-8:
Address Bank 31 F80h(2) F81h(2) F82h(2) F83h(2) F84h(2) F85h(2) F86h(2) F87h(2) F88h(2) F89h(2) F8Ah(2) F8Bh(2) F8Ch -- FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh Legend: Note 1: 2: -- STKPTR TOSL TOSH INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- Working Register -- GIE Unimplemented Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF -- -- BSR4 BSR3 BSR2 BSR1 BSR0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 0000 000x 0000 000u -- -- Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets
STATUS_ SHAD WREG_ SHAD BSR_ SHAD PCLATH_ SHAD FSR0L_ SHAD FSR0H_ SHAD FSR1L_ SHAD FSR1H_ SHAD
--
--
--
--
--
Z
DC
C
---- -xxx ---- -uuu 0000 0000 uuuu uuuu
Working Register Shadow -- -- -- -- Bank Select Register Shadow
---x xxxx ---u uuuu -xxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu -- --
Program Counter Latch High Register Shadow
Indirect Data Memory Address 0 Low Pointer Shadow Indirect Data Memory Address 0 High Pointer Shadow Indirect Data Memory Address 1 Low Pointer Shadow Indirect Data Memory Address 1 High Pointer Shadow Unimplemented -- -- -- Current Stack pointer Top-of-Stack Low byte -- Top-of-Stack High byte
---1 1111 ---1 1111 xxxx xxxx uuuu uuuu -xxx xxxx -uuu uuuu
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F/LF1827 only. These registers can be addressed from any bank.
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3.3 PCL and PCLATH
3.3.3 COMPUTED FUNCTION CALLS
The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-4 shows the five situations for the loading of the PC. A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. When performing a table read using a computed function CALL, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). If using the CALL instruction, the PCH<2:0> and PCL registers are loaded with the operand of the CALL instruction. PCH<6:3> is loaded with PCLATH<6:3>. The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address. A computed CALLW is accomplished by loading the W register with the desired address and executing CALLW. The PCL register is loaded with the value of W and PCH is loaded with PCLATH.
FIGURE 3-4:
14 PCH
LOADING OF PC IN DIFFERENT SITUATIONS
PCL 0
Instruction with PCL as Destination
PC
6 PCLATH 14
7
0
8
ALU Result PCL 0
GOTO, CALL
PC
PCH
3.3.4
BRANCHING
PCLATH PC
6 14
4
0
11
OPCODE <10:0> PCH PCL 0
CALLW
PCLATH
6
7
0
8
W PCL 0
The branching instructions add an offset to the PC. This allows relocatable code and code that crosses page boundaries. There are two forms of branching, BRW and BRA. The PC will have incremented to fetch the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be crossed. If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will be loaded with the address PC + 1 + W. If using BRA, the entire PC will be loaded with PC + 1 +, the signed value of the operand of the BRA instruction.
PC
14
PCH
BRW
PC + W 14 PCH PCL 0
BRA
15
PC
PC + OPCODE <8:0>
15
3.3.1
MODIFYING PCL
Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<14:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper 7 bits to the PCLATH register. When the lower 8 bits are written to the PCL register, all 15 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register.
3.3.2
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, "Implementing a Table Read" (DS00556).
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3.4 Stack
3.4.1 ACCESSING THE STACK
All devices have a 16-level x 15-bit wide hardware stack (refer to Figures 3-5 through 3-8). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer if the STVREN bit = 0 (Configuration Word 2). This means that after the stack has been PUSHed sixteen times, the seventeenth PUSH overwrites the value that was stored from the first PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). The STKOVF and STKUNF flag bits will be set on an Overflow/Underflow, regardless of whether the Reset is enabled. Note 1: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, CALLW, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address. The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is 5 bits to allow detection of overflow and underflow. Note: Care should be taken when modifying the STKPTR while interrupts are enabled.
During normal program operation, CALL, CALLW and Interrupts will increment STKPTR while RETLW, RETURN, and RETFIE will decrement STKPTR. At any time STKPTR can be inspected to see how much stack is left. The STKPTR always points at the currently used place on the stack. Therefore, a CALL or CALLW will increment the STKPTR and then write the PC, and a return will unload the PC and then decrement STKPTR. Reference Figure 3-5 through Figure 3-8 for examples of accessing the stack.
FIGURE 3-5:
ACCESSING THE STACK EXAMPLE 1
TOSH:TOSL
0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00
STKPTR = 0x1F
Stack Reset Disabled (STVREN = 0)
Initial Stack Configuration: After Reset, the stack is empty. The empty stack is initialized so the Stack Pointer is pointing at 0x1F. If the Stack Overflow/Underflow Reset is enabled, the TOSH/TOSL registers will return `0'. If the Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL registers will return the contents of stack address 0x0F.
TOSH:TOSL
0x1F
0x0000
STKPTR = 0x1F
Stack Reset Enabled (STVREN = 1)
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FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2
0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 TOSH:TOSL 0x00 Return Address STKPTR = 0x00 This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F).
FIGURE 3-7:
ACCESSING THE STACK EXAMPLE 3
0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 TOSH:TOSL 0x06 0x05 0x04 0x03 0x02 0x01 0x00 Return Address Return Address Return Address Return Address Return Address Return Address Return Address STKPTR = 0x06 After seven CALLs, or six CALLs and an interrupt, the stack looks like the figure on the left. A series of RETURN instructions will repeatedly place the return addresses into the Program Counter and pop the stack.
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FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4
0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 TOSH:TOSL 0x00
Return Address Return Address Return Address Return Address Return Address Return Address Return Address Return Address Return Address Return Address Return Address Return Address Return Address Return Address Return Address Return Address STKPTR = 0x10 When the stack is full, the next CALL or interrupt will set the Stack Pointer to 0x10. This is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. If the Stack Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will not be overwritten.
3.4.2
OVERFLOW/UNDERFLOW RESET
If the STVREN bit in Configuration Word 2 is set to `1', the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register.
3.5
Indirect Addressing
The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return `0' and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL. The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: * Traditional Data Memory * Linear Data Memory * Program Flash Memory
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FIGURE 3-9: INDIRECT ADDRESSING
0x0000 0x0000 Traditional Data Memory
0x0FFF 0x1000 0x1FFF 0x2000
0x0FFF Reserved
Linear Data Memory
0x29AF 0x29B0 FSR Address Range 0x7FFF 0x8000 Reserved 0x0000
Program Flash Memory
0xFFFF
0x7FFF
Note:
Not all memory regions are completely implemented. Consult device memory tables for memory limits.
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3.5.1 TRADITIONAL DATA MEMORY
The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers.
FIGURE 3-10:
TRADITIONAL DATA MEMORY MAP
Direct Addressing Indirect Addressing 0 7 0 0 0 FSRxH 0 Bank Select 1111 Location Select 0 7 FSRxL 0
4
BSR
0
6
From Opcode
Bank Select
Location Select 0x00 0000 0001 0010
0x7F Bank 0 Bank 1 Bank 2 Bank 31
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3.5.2 LINEAR DATA MEMORY 3.5.3 PROGRAM FLASH MEMORY
The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank. The 16 bytes of common memory are not included in the linear data memory region. To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the lower 8 bits of each memory location is accessible via INDF. Writing to the program Flash memory cannot be accomplished via the FSR/INDF interface. All instructions that access program Flash memory via the FSR/INDF interface will require one additional instruction cycle to complete.
FIGURE 3-11:
LINEAR DATA MEMORY MAP
0 7 FSRnL 0
FIGURE 3-12:
7 1
PROGRAM FLASH MEMORY MAP
0 7 FSRnL 0
FSRnH
7 FSRnH 001
Location Select Location Select 0x2000 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Bank 2 0x16F
0x8000
0x0000
Program Flash Memory (low 8 bits)
0xF20 Bank 30 0x29AF 0xF6F 0xFFFF 0x7FFF
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NOTES:
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4.0 DEVICE CONFIGURATION
Device Configuration consists of Configuration Word 1 and Configuration Word 2, Code Protection and Device ID.
4.1
Configuration Words
There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Word is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a '1'.
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REGISTER 4-1:
R/P-1/1 FCMEN bit 13 R/P-1/1 MCLRE bit 6 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 13 W = Writable bit x = Bit is unknown `0' = Bit is cleared FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled IESO: Internal External Switchover bit 1 = Internal/External Switchover mode is enabled 0 = Internal/External Switchover mode is disabled CLKOUTEN: Clock Out Enable bit If FOSC configuration bits are set to LP, XT, HS modes: This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin. All other FOSC modes: 1 = CLKOUT function is disabled. I/O function on the CLKOUT pin. 0 = CLKOUT function is enabled on the CLKOUT pin BOREN<1:0>: Brown-out Reset Enable bits(1) 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the BORCON register 00 = BOR disabled CPD: Data Code Protection bit(2) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled CP: Code Protection bit(3) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled MCLRE: RA5/MCLR/VPP Pin Function Select bit If LVP bit = 1: This bit is ignored. If LVP bit = 0: 1 = MCLR/VPP pin function is MCLR; Weak pull-up enabled. 0 = MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUA register. PWRTE: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled WDTE<1:0>: Watchdog Timer Enable bit 11 = WDT enabled 10 = WDT enabled while running and disabled in Sleep 01 = WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled Enabling Brown-out Reset does not automatically enable Power-up Timer. The entire data EEPROM will be erased when the code protection is turned off during an erase. The entire program memory will be erased when the code protection is turned off. U = Unimplemented bit, read as `1' -n/n = Value at POR and BOR/Value at all other Resets P = Programmable bit R/P-1/1 PWRTE R/P-1/1 WDTE1 R/P-1/1 WDTE0 R/P-1/1 FOSC2 R/P-1/1 FOSC1 R/P-1/1 FOSC0 bit 0
CONFIGURATION WORD 1
R/P-1/1 IESO R/P-1/1 CLKOUTEN R/P-1/1 BOREN1 R/P-1/1 BOREN0 R/P-1/1 CPD R/P-1/1 CP bit 7
bit 12
bit 11
bit 10-9
bit 8
bit 7
bit 6
bit 5
bit 4-3
Note 1: 2: 3:
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REGISTER 4-1:
bit 2-0
CONFIGURATION WORD 1 (CONTINUED)
FOSC<2:0>: Oscillator Selection bits 111 = ECH: External Clock, High-Power mode (4-32 MHz): device clock supplied to CLKIN pin 110 = ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin 101 = ECL: External Clock, Low-Power mode (0-0.5 MHz): device clock supplied to CLKIN pin 100 = INTOSC oscillator: I/O function on CLKIN pin 011 = EXTRC oscillator: External RC circuit connected to CLKIN pin 010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins 001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins 000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins Enabling Brown-out Reset does not automatically enable Power-up Timer. The entire data EEPROM will be erased when the code protection is turned off during an erase. The entire program memory will be erased when the code protection is turned off.
Note 1: 2: 3:
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REGISTER 4-2:
R/P-1/1 LVP(1) bit 13 U-1 -- bit 6 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 13 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `1' -n/n = Value at POR and BOR/Value at all other Resets P = Programmable bit U-1 -- R/P-1/1 U-1 -- U-1 -- R/P-1/1 WRT1 R/P-1/1 WRT0 bit 0
CONFIGURATION WORD 2
R/P-1/1 DEBUG(2) U-1 -- R/P-1/1 BORV R/P-1/1 STVREN R/P-1/1 PLLEN U-1 -- bit 7
Reserved
LVP: Low-Voltage Programming Enable bit(1) 1 = Low-voltage programming enabled 0 = High-voltage on MCLR must be used for programming DEBUG: In-Circuit Debugger Mode bit(2) 1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins 0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger Unimplemented: Read as `1' BORV: Brown-out Reset Voltage Selection bit 1 = Brown-out Reset voltage set to 1.9V (typical) 0 = Brown-out Reset voltage set to 2.5V (typical) STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Stack Overflow or Underflow will cause a Reset 0 = Stack Overflow or Underflow will not cause a Reset PLLEN: PLL Enable bit 1 = 4xPLL enabled 0 = 4xPLL disabled Unimplemented: Read as `1' Reserved: This location should be programmed to a `1'. Unimplemented: Read as `1' WRT<1:0>: Flash Memory Self-Write Protection bits 2 kW Flash memory (PIC16F/LF1826 only): 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to 7FFh may be modified by EECON control 01 = 000h to 3FFh write-protected, 400h to 7FFh may be modified by EECON control 00 = 000h to 7FFh write-protected, no addresses may be modified by EECON control 4 kW Flash memory (PIC16F/LF1827 only): 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to FFFh may be modified by EECON control 01 = 000h to 7FFh write-protected, 800h to FFFh may be modified by EECON control 00 = 000h to FFFh write-protected, no addresses may be modified by EECON control The LVP bit cannot be programmed to `0' when Programming mode is entered via LVP. The DEBUG bit in Configuration Word is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a '1'.
bit 12
bit 11 bit 10
bit 9
bit 8
bit 7-5 bit 4 bit 3-2 bit 1-0
Note 1: 2:
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4.2 Code Protection
Code protection allows the device to be protected from unauthorized access. Program memory protection and data EEPROM protection are controlled independently. Internal access to the program memory and data EEPROM are unaffected by any code protection setting.
4.2.1
PROGRAM MEMORY PROTECTION
The entire program memory space is protected from external reads and writes by the CP bit in Configuration Word 1. When CP = 0, external reads and writes of program memory are inhibited and a read will return all `0's. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write protection setting. See Section 4.3 "Write Protection" for more information.
4.2.2
DATA EEPROM PROTECTION
The entire data EEPROM is protected from external reads and writes by the CPD bit. When CPD = 0, external reads and writes of data EEPROM are inhibited. The CPU can continue to read and write data EEPROM regardless of the protection bit settings.
4.3
Write Protection
Write protection allows the device to be protected from unintended self-writes. Applications, such as bootloader software, can be protected while allowing other regions of the program memory to be modified. The WRT<1:0> bits in Configuration Word 2 define the size of the program memory block that is protected.
4.4
User ID
Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See Section 11.5 "User ID, Device ID and Configuration Word Access" for more information on accessing these memory locations. For more information on checksum calculation, see the "PIC16F/LF1826/27 Memory Programming Specification" (DS41390).
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4.5 Device ID and Revision ID
The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section 11.5 "User ID, Device ID and Configuration Word Access" for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID.
REGISTER 4-3:
R/P-1 DEV8 bit 13 R/P-1 DEV1 bit 6 Legend: R = Readable bit -n = Value at POR bit 13-5
DEVICEID: DEVICE ID REGISTER(1)
R/P-1 DEV7 R/P-1 DEV6 R/P-1 DEV5 R/P-1 DEV4 R/P-1 DEV3 R/P-1 DEV2 bit 7 R/P-1 DEV0 R/P-1 REV4 R/P-1 REV3 R/P-1 REV2 R/P-1 REV1 R/P-1 REV0 bit 0 P = Programmable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
DEV<8:0>: Device ID bits 100111100 = PIC16F1826 100111101 = PIC16F1827 101000100 = PIC16LF1826 101000101 = PIC16LF1827 REV<4:0>: Revision ID bits These bits are used to identify the revision.
bit 4-0
Note 1:
This location cannot be written.
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5.0
5.1
OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR)
Overview
The oscillator module can be configured in one of eight clock modes. 1. 2. 3. 4. 5. 6. 7. 8. ECL - External Clock Low Power mode (0 MHz to 0.5 MHz) ECM - External Clock Medium Power mode (0.5 MHz to 4 MHz) ECH - External Clock High Power mode (4 MHz to 32 MHz) LP - 32 kHz Low-Power Crystal mode. XT - Medium Gain Crystal or Ceramic Resonator Oscillator mode (up to 4 MHz) HS - High Gain Crystal or Ceramic Resonator mode (4 MHz to 20 MHz) RC - External Resistor-Capacitor (RC). INTOSC - Internal oscillator (31 kHz to 32 MHz).
The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 5-1 illustrates a block diagram of the oscillator module. Clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be supplied from one of two internal oscillators and PLL circuits, with a choice of speeds selectable via software. Additional clock features include: * Selectable system clock source between external or internal sources via software. * Two-Speed Start-up mode, which minimizes latency between external oscillator start-up and code execution. * Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch automatically to the internal oscillator. * Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources
Clock Source modes are selected by the FOSC<2:0> bits in the Configuration Word 1. The FOSC bits determine the type of oscillator that will be used when the device is first powered. The EC clock mode relies on an external logic level signal as the device clock source. The LP, XT, and HS clock modes require an external crystal or resonator to be connected to the device. Each mode is optimized for a different frequency range. The RC clock mode requires an external resistor and capacitor to set the oscillator frequency. The INTOSC internal oscillator block produces low, medium, and high frequency clock sources, designated LFINTOSC, MFINTOSC, and HFINTOSC. (see Internal Oscillator Block, Figure 5-1). A wide selection of device clock frequencies may be derived from these three clock sources.
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FIGURE 5-1: SIMPLIFIED PIC(R) MCU CLOCK SOURCE BLOCK DIAGRAM
External Oscillator OSC2 Sleep OSC1 Oscillator Timer1 T1OSO T1OSCEN Enable Oscillator FOSC<2:0> = 100 4 x PLL MUX T1OSC LP, XT, HS, RC, EC
Sleep CPU and Peripherals
T1OSI
IRCF<3:0> 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.25 kHz 31 kHz
Internal Oscillator
Internal Oscillator Block HFPLL 500 kHz Source 31 kHz Source Postscaler 16 MHz (HFINTOSC) 500 kHz (MFINTOSC)
MUX
Clock Control FOSC<2:0> SCS<1:0> Clock Source Option for other modules
31 kHz (LFINTOSC)
WDT, PWRT, Fail-Safe Clock Monitor Two-Speed Start-up and other modules
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5.2 Clock Source Types
Clock sources can be classified as external or internal. External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. Internal clock sources are contained internally within the oscillator module. The internal oscillator block has two internal oscillators and a dedicated phase-locked-loop (HFPLL) that are used to generate three internal system clock sources: the 16 MHz High-Frequency Internal Oscillator (HFINTOSC), 500 kHZ (MFINTOSC) and the 31 kHz Low-Frequency Internal Oscillator (LFINTOSC). The system clock can be selected between external or internal clock sources via the System Clock Select (SCS) bits in the OSCCON register. See Section 5.3 "Clock Switching" for additional information. The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC(R) MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.
FIGURE 5-2:
EXTERNAL CLOCK (EC) MODE OPERATION
OSC1/CLKIN PIC(R) MCU OSC2/CLKOUT
Clock from Ext. System
FOSC/4 or I/O(1) Note 1:
Output depends upon CLKOUTEN bit of the Configuration Word 1.
5.2.1
EXTERNAL CLOCK SOURCES 5.2.1.2 LP, XT, HS Modes
The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 5-3). The three modes select a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch crystals). XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification. HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting. Figure 5-3 and Figure 5-4 show typical circuits for quartz crystal and ceramic resonators, respectively.
An external clock source can be used as the device system clock by performing one of the following actions: * Program the FOSC<2:0> bits in the Configuration Word 1 to select an external clock source that will be used as the default system clock upon a device Reset. * Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to: - Timer1 Oscillator during run-time, or - An external clock source determined by the value of the FOSC bits. See Section 5.3 "Clock Switching"for more information.
5.2.1.1
EC Mode
The External Clock (EC) mode allows an externally generated logic level signal to be the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. Figure 5-2 shows the pin connections for EC mode. EC mode has 3 power modes to select from through Configuration Word 1: * High-power, 4-32 MHz (FOSC = 111) * Medium power, 0.5-4 MHz (FOSC = 110) * Low-power, 0-0.5 MHz (FOSC = 101)
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FIGURE 5-3: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE)
PIC(R) MCU
OSC1/CLKIN C1 Quartz Crystal RF(2) To Internal Logic Sleep C1
FIGURE 5-4:
CERAMIC RESONATOR OPERATION (XT OR HS MODE)
PIC(R) MCU
OSC1/CLKIN To Internal Logic RP(3) RF(2) Sleep
C2
RS(1)
OSC2/CLKOUT
C2 Ceramic RS(1) Resonator
OSC2/CLKOUT
Note 1: 2:
A series resistor (RS) may be required for quartz crystals with low drive level. The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M.
Note 1:
A series resistor (RS) may be required for ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M. 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation.
Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Applications Notes: * AN826, "Crystal Oscillator Basics and Crystal Selection for rfPIC(R) and PIC(R) Devices" (DS00826) * AN849, "Basic PIC(R) Oscillator Design" (DS00849) * AN943, "Practical PIC(R) Oscillator Analysis and Design" (DS00943) * AN949, "Making Your Oscillator Work" (DS00949)
5.2.1.3
Oscillator Start-up Timer (OST)
If the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module. In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section 5.4 "Two-Speed Clock Start-up Mode").
5.2.1.4
4X PLL
The oscillator module contains a 4X PLL that can be used with both external and internal clock sources to provide a system clock source. The input frequency for the 4X PLL must fall within specifications. See the PLL Clock Timing Specifications in Section 29.0 "Electrical Specifications" The 4X PLL may be enabled for use by one of two methods: 1. 2. Program the PLLEN bit in Configuration Word 2 to a `1'. Write the SPLLEN bit in the OSCCON register to a `1'. If the PLLEN bit in Configuration Word 2 is programmed to a `1', then the value of SPLLEN is ignored.
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5.2.1.5 TIMER1 Oscillator 5.2.1.6 External RC Mode
The Timer1 Oscillator is a separate crystal oscillator that is associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the T1OSO and T1OSI device pins. The Timer1 Oscillator can be used as an alternate system clock source and can be selected during run-time using clock switching. Refer to Section 5.3 "Clock Switching" for more information. The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. The RC circuit connects to OSC1. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the state of the CLKOUTEN bit in Configuration Word 1. Figure 5-5 shows the external RC mode connections.
FIGURE 5-5:
QUARTZ CRYSTAL OPERATION (TIMER1 OSCILLATOR)
PIC(R)
T1OSI
FIGURE 5-6:
VDD
EXTERNAL RC MODES
PIC(R) MCU
MCU
REXT OSC1/CLKIN
To Internal Logic
C1 32.768 kHz Quartz Crystal
Internal Clock
CEXT VSS FOSC/4 or I/O(1) OSC2/CLKOUT
C2
T1OSO
Recommended values: 10 k REXT 100 k, <3V 3 k REXT 100 k, 3-5V CEXT > 20 pF, 2-5V
Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Applications Notes: * AN826, "Crystal Oscillator Basics and Crystal Selection for rfPIC(R) and PIC(R) Devices" (DS00826) * AN849, "Basic PIC(R) Oscillator Design" (DS00849) * AN943, "Practical PIC(R) Oscillator Analysis and Design" (DS00943) * AN949, "Making Your Oscillator Work" (DS00949) * TB097, "Interfacing a Micro Crystal MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS" (DS91097) * AN1288, "Design Practices for Low-Power External Oscillators" (DS01288)
Note 1:
Output depends upon CLKOUTEN bit of the Configuration Word 1.
The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are: * threshold voltage variation * component tolerances * packaging variations in capacitance The user also needs to take into account variation due to tolerance of external RC components used.
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5.2.2 INTERNAL CLOCK SOURCES 5.2.2.1 HFINTOSC
The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: * Program the FOSC<2:0> bits in Configuration Word 1 to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. * Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See Section 5.3 "Clock Switching"for more information. In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the state of the CLKOUTEN bit in Configuration Word 1. The internal oscillator block has two independent oscillators and a dedicated Phase-Locked Loop, HFPLL that can produce one of three internal system clock sources. 1. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at 16 MHz. The HFINTOSC source is generated from the 500 kHz MFINTOSC source and the dedicated Phase-Locked Loop, HFPLL. The frequency of the HFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 5-3). The MFINTOSC (Medium-Frequency Internal Oscillator) is factory calibrated and operates at 500 kHz. The frequency of the MFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 5-3). The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at 31 kHz. The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 16 MHz internal clock source. The frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register 5-3). The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). One of nine frequencies derived from the HFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 5.2.2.7 "Internal Oscillator Clock Switch Timing" for more information. The HFINTOSC is enabled by: * Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and * FOSC<2:0> = 100, or * Set the System Clock Source (SCS) bits of the OSCCON register to `1x'. The High Frequency Internal Oscillator Ready bit (HFIOFR) of the OSCSTAT register indicates when the HFINTOSC is running and can be utilized. The High Frequency Internal Oscillator Status Locked bit (HFIOFL) of the OSCSTAT register indicates when the HFINTOSC is running within 2% of its final value. The High Frequency Internal Oscillator Status Stable bit (HFIOFS) of the OSCSTAT register indicates when the HFINTOSC is running within 0.5% of its final value.
5.2.2.2
MFINTOSC
2.
The Medium-Frequency Internal Oscillator (MFINTOSC) is a factory calibrated 500 kHz internal clock source. The frequency of the MFINTOSC can be altered via software using the OSCTUNE register (Register 5-3). The output of the MFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). One of nine frequencies derived from the MFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 5.2.2.7 "Internal Oscillator Clock Switch Timing" for more information. The MFINTOSC is enabled by: * Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and * FOSC<2:0> = 100, or * Set the System Clock Source (SCS) bits of the OSCCON register to `1x' The Medium Frequency Internal Oscillator Ready bit (MFIOFR) of the OSCSTAT register indicates when the MFINTOSC is running and can be utilized.
3.
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5.2.2.3 Internal Oscillator Frequency Adjustment 5.2.2.5 Internal Oscillator Frequency Selection
The 500 kHz internal oscillator is factory calibrated. This internal oscillator can be adjusted in software by writing to the OSCTUNE register (Register 5-3). Since the HFINTOSC and MFINTOSC clock sources are derived from the 500 kHz internal oscillator a change in the OSCTUNE register value will apply to both. The default value of the OSCTUNE register is `0'. The value is a 6-bit two's complement number. A value of 1Fh will provide an adjustment to the maximum frequency. A value of 20h will provide an adjustment to the minimum frequency. When the OSCTUNE register is modified, the oscillator frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register. The output of the 16 MHz HFINTOSC and 31 kHz LFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). The Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register select the frequency output of the internal oscillators. One of the following frequencies can be selected via software: * * * * * * * * * * * * 32 MHz (requires 4X PLL) 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz (Default after Reset) 250 kHz 125 kHz 62.5 kHz 31.25 kHz 31 kHz (LFINTOSC) Note: Following any Reset, the IRCF<3:0> bits of the OSCCON register are set to `0111' and the frequency selection is set to 500 kHz. The user can modify the IRCF bits to select a different frequency.
5.2.2.4
LFINTOSC
The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). Select 31 kHz, via software, using the IRCF<3:0> bits of the OSCCON register. See Section 5.2.2.7 "Internal Oscillator Clock Switch Timing" for more information. The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The LFINTOSC is enabled by selecting 31 kHz (IRCF<3:0> bits of the OSCCON register = 000) as the system clock source (SCS bits of the OSCCON register = 1x), or when any of the following are enabled: * Configure the IRCF<3:0> bits of the OSCCON register for the desired LF frequency, and * FOSC<2:0> = 100, or * Set the System Clock Source (SCS) bits of the OSCCON register to `1x' Peripherals that use the LFINTOSC are: * Power-up Timer (PWRT) * Watchdog Timer (WDT) * Fail-Safe Clock Monitor (FSCM) The Low Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running and can be utilized.
The IRCF<3:0> bits of the OSCCON register allow duplicate selections for some frequencies. These duplicate choices can offer system design trade-offs. Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transition times can be obtained between frequency changes that use the same oscillator source.
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5.2.2.6 32 MHz Internal Oscillator Frequency Selection 5.2.2.7 Internal Oscillator Clock Switch Timing
The Internal Oscillator Block can be used with the 4X PLL associated with the External Oscillator Block to produce a 32 MHz internal system clock source. The following settings are required to use the 32 MHz internal clock source: * The FOSC bits in Configuration Word 1 must be set to use the INTOSC source as the device system clock (FOSC<2:0> = 100). * The SCS bits in the OSCCON register must be cleared to use the clock determined by FOSC<2:0> in Configuration Word 1 (SCS<1:0> = 00). * The IRCF bits in the OSCCON register must be set to the 8 MHz HFINTOSC set to use (IRCF<3:0> = 1110). * The SPLLEN bit in the OSCCON register must be set to enable the 4xPLL, or the PLLEN bit of the Configuration Word 2 must be programmed to a `1'. Note: When using the PLLEN bit of the Configuration Word 2, the 4xPLL cannot be disabled by software and the 8 MHz HFINTOSC option will no longer be available. When switching between the HFINTOSC, MFINTOSC and the LFINTOSC, the new oscillator may already be shut down to save power (see Figure 5-6). If this is the case, there is a delay after the IRCF<3:0> bits of the OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will reflect the current active status of the HFINTOSC, MFINTOSC and LFINTOSC oscillators. The sequence of a frequency selection is as follows: 1. 2. 3. 4. IRCF<3:0> bits of the OSCCON register are modified. If the new clock is shut down, a clock start-up delay is started. Clock switch circuitry waits for a falling edge of the current clock. The current clock is held low and the clock switch circuitry waits for a rising edge in the new clock. The new clock is now active. The OSCSTAT register is updated as required. Clock switch is complete.
5. 6. 7.
See Figure 5-6 for more details. If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in Table 5-1. Start-up delay specifications are located in the oscillator tables of Section 29.0 "Electrical Specifications".
The 4xPLL is not available for use with the internal oscillator when the SCS bits of the OSCCON register are set to `1x'. The SCS bits must be set to `00' to use the 4xPLL with the internal oscillator.
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FIGURE 5-7: INTERNAL OSCILLATOR SWITCH TIMING
HFINTOSC/ MFINTOSC HFINTOSC/ MFINTOSC LFINTOSC IRCF <3:0> System Clock
LFINTOSC (FSCM and WDT disabled)
Start-up Time
2-cycle Sync
Running
0
0
HFINTOSC/ MFINTOSC HFINTOSC/ MFINTOSC LFINTOSC IRCF <3:0> System Clock
LFINTOSC (Either FSCM or WDT enabled)
2-cycle Sync
Running
0
0
LFINTOSC LFINTOSC
HFINTOSC/MFINTOSC
LFINTOSC turns off unless WDT or FSCM is enabled
Start-up Time
2-cycle Sync
Running
HFINTOSC/ MFINTOSC IRCF <3:0> System Clock
=0
0
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5.3 Clock Switching
5.3.3 TIMER1 OSCILLATOR
The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: * Default system oscillator determined by FOSC bits in Configuration Word 1 * Timer1 32 kHz crystal oscillator * Internal Oscillator Block (INTOSC) The Timer1 Oscillator is a separate crystal oscillator associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the T1OSO and T1OSI device pins. The Timer1 oscillator is enabled using the T1OSCEN control bit in the T1CON register. See Section 21.0 "Timer1 Module with Gate Control" for more information about the Timer1 peripheral.
5.3.1
SYSTEM CLOCK SELECT (SCS) BITS
5.3.4
TIMER1 OSCILLATOR READY (T1OSCR) BIT
The System Clock Select (SCS) bits of the OSCCON register selects the system clock source that is used for the CPU and peripherals. * When the SCS bits of the OSCCON register = 00, the system clock source is determined by value of the FOSC<2:0> bits in the Configuration Word 1. * When the SCS bits of the OSCCON register = 01, the system clock source is the Timer1 oscillator. * When the SCS bits of the OSCCON register = 1x, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<3:0> bits of the OSCCON register. After a Reset, the SCS bits of the OSCCON register are always cleared. Note: Any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bits of the OSCCON register. The user can monitor the OSTS bit of the OSCSTAT register to determine the current system clock source.
The user must ensure that the Timer1 Oscillator is ready to be used before it is selected as a system clock source. The Timer1 Oscillator Ready (T1OSCR) bit of the OSCSTAT register indicates whether the Timer1 oscillator is ready to be used. After the T1OSCR bit is set, the SCS bits can be configured to select the Timer1 oscillator.
When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 5-1.
5.3.2
OSCILLATOR START-UP TIME-OUT STATUS (OSTS) BIT
The Oscillator Start-up Time-out Status (OSTS) bit of the OSCSTAT register indicates whether the system clock is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word 1, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. The OST does not reflect the status of the Timer1 Oscillator.
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5.4 Two-Speed Clock Start-up Mode
5.4.1
Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC internal oscillator block as the clock source and go back to Sleep without waiting for the external oscillator to become stable. Two-Speed Start-up provides benefits when the oscillator module is configured for LP, XT, or HS modes. The Oscillator Start-up Timer (OST) is enabled for these modes and must count 1024 oscillations before the oscillator can be used as the system clock source. If the oscillator module is configured for any mode other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep. If the OST count reaches 1024 before the device enters Sleep mode, the OSTS bit of the OSCSTAT register is set and program execution switches to the external oscillator. However, the system may never operate from the external oscillator if the time spent awake is very short. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCSTAT register to remain clear.
TWO-SPEED START-UP MODE CONFIGURATION
Two-Speed Start-up mode is configured by the following settings: * IESO (of the Configuration Word 1) = 1; Internal/External Switchover bit (Two-Speed Start-up mode enabled). * SCS (of the OSCCON register) = 00. * FOSC<2:0> bits in the Configuration Word 1 configured for LP, XT or HS mode. Two-Speed Start-up mode is entered after: * Power-on Reset (POR) and, if enabled, after Power-up Timer (PWRT) has expired, or * Wake-up from Sleep.
TABLE 5-1:
Switch From Sleep/POR Sleep/POR LFINTOSC Sleep/POR Any clock source Any clock source Any clock source PLL inactive Note 1:
OSCILLATOR SWITCHING DELAYS
Switch To LFINTOSC(1) MFINTOSC(1) HFINTOSC(1) RC(1) Frequency 31 kHz 31.25 kHz-500 kHz 31.25 kHz-16 MHz DC - 32 MHz DC - 32 MHz 32 kHz-20 MHz 31.25 kHz-500 kHz 31.25 kHz-16 MHz 31 kHz 32 kHz 16-32 MHz Oscillator Delay Oscillator Warm-up Delay (TWARM) 2 cycles 1 cycle of each 1024 Clock Cycles (OST) 2 s (approx.) 1 cycle of each 1024 Clock Cycles (OST) 2 ms (approx.)
EC, RC(1) EC, Timer1 Oscillator LP, XT, HS(1) MFINTOSC(1) HFINTOSC(1) LFINTOSC(1) Timer1 Oscillator PLL active
PLL inactive.
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5.4.2
1. 2.
TWO-SPEED START-UP SEQUENCE
5.4.3
CHECKING TWO-SPEED CLOCK STATUS
3. 4. 5. 6. 7.
Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register. OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source.
Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word 1, or the internal oscillator.
FIGURE 5-8:
TWO-SPEED START-UP
INTOSC T TOST OSC1 0 1 1022 1023
OSC2 Program Counter PC - N PC PC + 1
System Clock
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5.5 Fail-Safe Clock Monitor
5.5.3 FAIL-SAFE CONDITION CLEARING
The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Word 1. The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, Timer1 Oscillator and RC). The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register. When the SCS bits are changed, the OST is restarted. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared and the device will be operating from the external clock source. The Fail-Safe condition must be cleared before the OSFIF flag can be cleared.
FIGURE 5-9:
FSCM BLOCK DIAGRAM
Clock Monitor Latch S Q
5.5.4
RESET OR WAKE-UP FROM SLEEP
External Clock
LFINTOSC Oscillator 31 kHz (~32 s)
/ 64 488 Hz (~2 ms)
R
Q
The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. When the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing code while the OST is operating.
Clock Failure Detected
Sample Clock
Note:
5.5.1
FAIL-SAFE DETECTION
The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure 5-8. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low.
Due to the wide range of oscillator start-up times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the Status bits in the OSCSTAT register to verify the oscillator start-up and that the system clock switchover has successfully completed.
5.5.2
FAIL-SAFE OPERATION
When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR2 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs.
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FIGURE 5-10:
Sample Clock System Clock Output Clock Monitor Output (Q) OSCFIF Oscillator Failure
FSCM TIMING DIAGRAM
Failure Detected
Test Note:
Test
Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.
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5.6 Oscillator Control Registers
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 -- R/W-0/0 R/W-0/0 bit 0 IRCF<3:0> SCS<1:0>
REGISTER 5-1:
R/W-0/0 SPLLEN bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
SPLLEN: Software PLL Enable bit If PLLEN in Configuration Word 1 = 1: SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements) If PLLEN in Configuration Word 1 = 0: 1 = 4x PLL Is enabled 0 = 4x PLL is disabled
bit 6-3
IRCF<3:0>: Internal Oscillator Frequency Select bits 000x =31 kHz LF 0010 =31.25 kHz MF 0011 =31.25 kHz HF(1) 0100 =62.5 kHz MF 0101 =125 kHz MF 0110 =250 kHz MF 0111 =500 kHz MF (default upon Reset) 1000 =125 kHz HF(1) 1001 =250 kHz HF(1) 1010 =500 kHz HF(1) 1011 =1 MHz HF 1100 =2 MHz HF 1101 =4 MHz HF 1110 =8 MHz or 32 MHz HF(see Section 5.2.2.1 "HFINTOSC") 1111 =16 MHz HF Unimplemented: Read as `0' SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Timer1 oscillator 00 = Clock determined by FOSC<2:0> in Configuration Word 1. Duplicate frequency derived from HFINTOSC.
bit 2 bit 1-0
Note 1:
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REGISTER 5-2:
R-1/q T1OSCR bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared T1OSCR: Timer1 Oscillator Ready bit If T1OSCEN = 1: 1 = Timer1 oscillator is ready 0 = Timer1 oscillator is not ready If T1OSCEN = 0: 1 = Timer1 clock source is always ready PLLR 4x PLL Ready bit 1 = 4x PLL is ready 0 = 4x PLL is not ready OSTS: Oscillator Start-up Time-out Status bit 1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Word 1 0 = Running from an internal oscillator (FOSC<2:0> = 100) HFIOFR: High Frequency Internal Oscillator Ready bit 1 = HFINTOSC is ready 0 = HFINTOSC is not ready HFIOFL: High Frequency Internal Oscillator Locked bit 1 = HFINTOSC is at least 2% accurate 0 = HFINTOSC is not 2% accurate MFIOFR: Medium Frequency Internal Oscillator Ready bit 1 = MFINTOSC is ready 0 = MFINTOSC is not ready LFIOFR: Low Frequency Internal Oscillator Ready bit 1 = LFINTOSC is ready 0 = LFINTOSC is not ready HFIOFS: High Frequency Internal Oscillator Stable bit 1 = HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets q = Conditional
OSCSTAT: OSCILLATOR STATUS REGISTER
R-0/q PLLR R-q/q OSTS R-0/q HFIOFR R-0/q HFIOFL R-q/q MFIOFR R-0/0 LFIOFR R-0/q HFIOFS bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 5-3:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6 bit 5-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0' TUN<4:0>: Frequency Tuning bits 011111 = Maximum frequency 011110 = * * * 000001 = 000000 = Oscillator module is running at the factory-calibrated frequency. 111111 = * * * 100000 = Minimum frequency U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
OSCTUNE: OSCILLATOR TUNING REGISTER
U-0 -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 bit 0 TUN<5:0>
TABLE 5-2:
Name OSCCON OSCSTAT OSCTUNE PIE2 PIR2 T1CON Legend: Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Bit 7 SPLLEN T1OSCR -- OSFIE OSFIF Bit 6 IRCF3 PLLR -- C2IE C2IF Bit 5 IRCF2 OSTS TUN5 C1IE C1IF T1CKPS1 Bit 4 IRCF1 HFIOFR TUN4 EEIE EEIF T1CKPS0 Bit 3 IRCF0 HFIOFL TUN3 BCL1IE BCL1IF T1OSCEN Bit 2 -- MFIOFR TUN2 -- -- T1SYNC Bit 1 SCS1 LFIOFR TUN1 -- -- -- Bit 0 SCS0 HFIOFS TUN0 CCP2IE(1) CCP2IF
(1)
Register on Page 69 70 71 94 97 187
TMR1CS1 TMR1CS0
TMR1ON
-- = unimplemented locations read as `0'. Shaded cells are not used by clock sources. PIC16F/LF1827 only.
TABLE 5-3:
Name Bits 13:8 7:0
SUMMARY OF CONFIGURATION WORD ASSOCIATED WITH CLOCK SOURCES
Bit -/7 -- CP Bit -/6 -- MCLRE Bit 13/5 FCMEN PWRTE Bit 12/4 IESO WDTE1 Bit 11/3 CLKOUTEN WDTE0 Bit 10/2 BOREN1 FOSC2 Bit 9/1 BOREN0 FOSC1 Bit 8/0 CPD FOSC0 Register on Page 50
CONFIG1 Legend:
-- = unimplemented locations read as `0'. Shaded cells are not used by clock sources.
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6.0 REFERENCE CLOCK MODULE
6.3 Conflicts with the CLKR pin
The Reference Clock module provides the ability to send a divided clock to the clock output pin of the device (CLKR) and provide a secondary internal clock source to the Modulator module. This module is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application. The reference clock module includes the following features: * * * * * * System clock is the source Available in all oscillator configurations Programmable clock divider Output enable to a port pin Selectable duty cycle Slew rate control There are two cases when the reference clock output signal cannot be output to the CLKR pin, if: * LP, XT, or HS oscillator mode is selected. * CLKOUT function is enabled. Even if either of these cases are true, the module can still be enabled and the reference clock signal may be used in conjunction with the Modulator module.
6.3.1
OSCILLATOR MODES
If LP, XT, or HS oscillator modes are selected, the OSC2/CLKR pin must be used as an oscillator input pin and the CLKR output cannot be enabled. See Section 5.2 "Clock Source Types" for more information on different oscillator modes.
The Reference Clock module is controlled by the CLKRCON register (Register 6-1) and is enabled when setting the CLKREN bit. To output the divided clock signal to the CLKR port pin, the CLKROE bit must be set. The CLKRDIV<2:0> bits enable the selection of 8 different clock divider options. The CLKRDC<1:0> bits can be used to modify the duty cycle of the output clock(1). The CLKRSLR bit controls slew rate limiting. Note 1: If the base clock rate is selected without a divider, the output clock will always have a duty cycle equal to that of the source clock, unless a 0% duty cycle is selected. If the clock divider is set to base clock/2, then 25% and 75% duty cycle accuracy will be dependent upon the source clock. For information on using the reference clock output with the Modulator module, see Section 22.0 "Data Signal Modulator".
6.3.2
CLKOUT FUNCTION
The CLKOUT function has a higher priority than the Reference Clock module. Therefore, if the CLKOUT function is enabled by the CLKOUTEN bit in Configuration Word 1, FOSC/4 will always be output on the port pin. Reference Section 4.0 "Device Configuration" for more information.
6.4
Operation During Sleep
As the Reference Clock module relies on the system clock as its source, and the system clock is disabled in Sleep, the module does not function in Sleep, even if an external clock source or the Timer1 clock source is configured as the system clock. The module outputs will remain in their current state until the device exits Sleep.
6.1
Slew Rate
The slew rate limitation on the output port pin can be disabled. The Slew Rate limitation can be removed by clearing the CLKRSLR bit in the CLKRCON register.
6.2
Effects of a Reset
Upon any device Reset, the reference clock module is disabled. The user's firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values.
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REGISTER 6-1:
R/W-0/0 CLKREN bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared CLKREN: Reference Clock Module Enable bit 1 = Reference Clock module is enabled 0 = Reference Clock module is disabled CLKROE: Reference Clock Output Enable bit(3) 1 = Reference Clock output is enabled on CLKR pin 0 = Reference Clock output disabled on CLKR pin CLKRSLR: Reference Clock Slew Rate Control limiting enable bit 1 = Slew Rate limiting is enabled 0 = Slew Rate limiting is disabled CLKRDC<1:0>: Reference Clock Duty Cycle bits 11 = Clock outputs duty cycle of 75% 10 = Clock outputs duty cycle of 50% 01 = Clock outputs duty cycle of 25% 00 = Clock outputs duty cycle of 0% CLKRDIV<2:0> Reference Clock Divider bits 111 = Base clock value divided by 128 110 = Base clock value divided by 64 101 = Base clock value divided by 32 100 = Base clock value divided by 16 011 = Base clock value divided by 8 010 = Base clock value divided by 4 001 = Base clock value divided by 2(1) 000 = Base clock value(2) U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
CLKRCON: REFERENCE CLOCK CONTROL REGISTER
R/W-0/0 CLKROE R/W-1/1 CLKRSLR R/W-1/1 R/W-0/0 R/W-0/0 R/W-0/0 CLKRDIV<2:0> bit 0 R/W-0/0 CLKRDC<1:0>
bit 6
bit 5
bit 4-3
bit 2-0
Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle. 2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0% is selected. 3: To route CLKR to pin, CLKOUTEN of Configuration Word 1 = 1 is required. CLKOUTEN of Configuration Word 1 = 0 will result in FOSC/4. See Section 6.3 "Conflicts with the CLKR pin" for details.
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TABLE 6-1:
Name CLKRCON Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH REFERENCE CLOCK SOURCES
Bit 7 CLKREN Bit 6 CLKROE Bit 5 CLKRSLR Bit 4 CLKRDC1 Bit 3 CLKRDC0 Bit 2 CLKRDIV2 Bit 1 Bit 0 Register on Page 74
CLKRDIV1 CLKRDIV0
-- = unimplemented locations read as `0'. Shaded cells are not used by reference clock sources.
TABLE 6-2:
Name Bits 13:8 7:0
SUMMARY OF CONFIGURATION WORD WITH REFERENCE CLOCK SOURCES
Bit -/7 -- CP Bit -/6 -- MCLRE Bit 13/5 FCMEN PWRTE Bit 12/4 IESO WDTE1 Bit 11/3 CLKOUTEN WDTE0 Bit 10/2 BOREN1 FOSC2 Bit 9/1 BOREN0 FOSC1 Bit 8/0 CPD FOSC0 Register on Page 50
CONFIG1 Legend:
-- = unimplemented locations read as `0'. Shaded cells are not used by reference clock sources.
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NOTES:
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7.0
* * * * * * * *
RESETS
There are multiple ways to reset this device: Power-on Reset (POR) Brown-out Reset (BOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit
To allow VDD to stabilize, an optional power-up timer can be enabled to extend the Reset time after a BOR or POR event. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 7-1.
FIGURE 7-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Programming Mode Exit RESET Instruction Stack Stack Overflow/Underflow Reset Pointer External Reset MCLR Sleep WDT Time-out Power-on Reset VDD Brown-out Reset BOR Enable Device Reset MCLRE
PWRT Zero LFINTOSC 64 ms
PWRTEN
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7.1 Power-on Reset (POR) 7.2 Brown-Out Reset (BOR)
The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when Vdd reaches a selectable minimum level. Between the POR and BOR, complete voltage range coverage for execution protection can be implemented. The Brown-out Reset module has four operating modes controlled by the BOREN<1:0> bits in Configuration Word 1. The four operating modes are: * * * * BOR is always on BOR is off when in Sleep BOR is controlled by software BOR is always off
7.1.1
POWER-UP TIMER (PWRT)
The Power-up Timer provides a nominal 64 ms timeout on POR or Brown-out Reset. The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the VDD to rise to an acceptable level. The Power-up Timer is enabled by clearing the PWRTE bit in Configuration Word 1. The Power-up Timer starts after the release of the POR and BOR. For additional information, refer to Application Note AN607, "Power-up Trouble Shooting" (DS00607).
Refer to Table 7-3 for more information. The Brown-out Reset voltage level is selectable by configuring the BORV bit in Configuration Word 2. A VDD noise rejection filter prevents the BOR from triggering on small events. If VDD falls below VBOR for a duration greater than parameter TBORDC, the device will reset. See Figure 7-3 for more information.
TABLE 7-1:
BOR OPERATING MODES
SBOREN Device Mode BOR Mode Device Device Operation upon Operation upon wake- up from release of POR Sleep Waits for BOR ready(1) Waits for BOR ready Begins immediately Begins immediately Begins immediately
BOREN Config bits BOR_ON (11) BOR_NSLEEP (10) BOR_NSLEEP (10) BOR_SBOREN (01) BOR_SBOREN (01) BOR_OFF (00)
X X X 1 0 X
X Awake Sleep X X X
Active Active Disabled Active Disabled Disabled
Note 1: Even though this case specifically waits for the BOR, the BOR is already operating, so there is no delay in start-up.
7.2.1
BOR IS ALWAYS ON
7.2.3
BOR CONTROLLED BY SOFTWARE
When the BOREN bits of Configuration Word 1 are set to `11', the BOR is always on. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep.
When the BOREN bits of Configuration Word 1 are set to `01', the BOR is controlled by the SBOREN bit of the BORCON register. The device start-up is not delayed by the BOR ready condition or the VDD level. BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the BORRDY bit of the BORCON register. BOR protection is unchanged by Sleep.
7.2.2
BOR IS OFF IN SLEEP
When the BOREN bits of Configuration Word 1 are set to `10', the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready.
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FIGURE 7-2:
SBOREN
BROWN-OUT READY
BORRDY
TBORRDY
BOR Protection Active
FIGURE 7-3:
VDD
BROWN-OUT SITUATIONS
VBOR
Internal Reset VDD
TPWRT(1)
VBOR < TPWRT
Internal Reset
TPWRT(1)
VDD
VBOR
Internal Reset Note 1: TPWRT delay only if PWRTE bit is programmed to `0'.
TPWRT(1)
REGISTER 7-1:
R/W-1/u SBOREN bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7
BORCON: BROWN-OUT RESET CONTROL REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R-q/u BORRDY bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition
SBOREN: Software Brown-out Reset Enable bit If BOREN <1:0> in Configuration Word 1 01: SBOREN is read/write, but has no effect on the BOR. If BOREN <1:0> in Configuration Word 1 = 01: 1 = BOR Enabled 0 = BOR Disabled Unimplemented: Read as `0' BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive
bit 6-1 bit 0
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7.3 MCLR 7.7 Programming Mode Exit
The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE bit of Configuration Word 1 and the LVP bit of Configuration Word 2 (Table 7-2). Upon exit of Programming mode, the device will behave as if a POR had just occurred.
7.8
Power-Up Timer
TABLE 7-2:
MCLRE 0 1 x
MCLR CONFIGURATION
LVP 0 0 1 MCLR Disabled Enabled Enabled
The Power-up Timer optionally delays device execution after a BOR or POR event. This timer is typically used to allow VDD to stabilize before allowing the device to start running. The Power-up Timer is controlled by the PWRTE bit of Configuration Word 1.
7.3.1
MCLR ENABLED
7.9
Start-up Sequence
When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected to VDD through an internal weak pull-up. The device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. Note: A Reset does not drive the MCLR pin low.
Upon the release of a POR or BOR, the following must occur before the device will begin executing: 1. 2. 3. Power-up Timer runs to completion (if enabled). Oscillator start-up timer runs to completion (if required for oscillator source). MCLR must be released (if enabled).
7.3.2
MCLR DISABLED
When MCLR is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. See Section 12.2 "PORTA Registers" for more information.
The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See Section 5.0 "Oscillator Module (With Fail-Safe Clock Monitor)" for more information. The Power-up Timer and oscillator start-up timer run independently of MCLR Reset. If MCLR is kept low long enough, the Power-up Timer and oscillator startup timer will expire. Upon bringing MCLR high, the device will begin execution immediately (see Figure 74). This is useful for testing purposes or to synchronize more than one device operating in parallel.
7.4
Watchdog Timer (WDT) Reset
The Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The TO and PD bits in the STATUS register are changed to indicate the WDT Reset. See Section "" for more information.
7.5
RESET Instruction
A RESET instruction will cause a device Reset. The RI bit in the PCON register will be set to `0'. See Table 7-4 for default conditions after a RESET instruction has occurred.
7.6
Stack Overflow/Underflow Reset
The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits of the PCON register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration Word 2. See Section 3.4.2 "Overflow/Underflow Reset" for more information.
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FIGURE 7-4: RESET START-UP SEQUENCE
VDD Internal POR TPWRT Power-Up Timer MCLR TMCLR Internal RESET
Oscillator Modes
External Crystal Oscillator Start-Up Timer Oscillator FOSC TOST
Internal Oscillator Oscillator FOSC
External Clock (EC) CLKIN
FOSC
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7.10 Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table 7-3 and Table 7-4 show the Reset conditions of these registers.
TABLE 7-3:
0 0 0 0 u u u u u u 1 u 0 0 0 0 u u u u u u u 1
RESET STATUS BITS AND THEIR SIGNIFICANCE
RMCLR 1 1 1 1 u u u 0 0 u u u RI 1 1 1 1 u u u u u 0 u u POR 0 0 0 u u u u u u u u u BOR x x x 0 u u u u u u u u TO 1 0 x 1 0 0 1 u 1 u u u PD 1 x 0 1 u 0 0 u 0 u u u Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR Brown-out Reset WDT Reset WDT Wake-up from Sleep Interrupt Wake-up from Sleep MCLR Reset during normal operation MCLR Reset during Sleep RESET Instruction Executed Stack Overflow Reset (STVREN = 1) Stack Underflow Reset (STVREN = 1) Condition
STKOVF STKUNF
TABLE 7-4:
RESET CONDITION FOR SPECIAL REGISTERS(2)
Condition Program Counter 0000h 0000h 0000h 0000h PC + 1 0000h PC + 1
(1)
STATUS Register ---1 1000 ---u uuuu ---1 0uuu ---0 uuuu ---0 0uuu ---1 1uuu ---1 0uuu ---u uuuu ---u uuuu ---u uuuu
PCON Register 00-- 110x uu-- 0uuu uu-- 0uuu uu-- uuuu uu-- uuuu 00-- 11u0 uu-- uuuu uu-- u0uu 1u-- uuuu u1-- uuuu
Power-on Reset MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset WDT Wake-up from Sleep Brown-out Reset Interrupt Wake-up from Sleep RESET Instruction Executed Stack Overflow Reset (STVREN = 1) Stack Underflow Reset (STVREN = 1)
0000h 0000h 0000h
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0'. Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1. 2: If a Status bit is not implemented, that bit will be read as `0'.
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7.11 Power Control (PCON) Register
The Power Control (PCON) register contains flag bits to differentiate between a: * * * * * * Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) Stack Overflow Reset (STKOVF) Stack Underflow Reset (STKUNF) MCLR Reset (RMCLR)
The PCON register bits are shown in Register 7-2.
REGISTER 7-2:
R/W/HS-0/q STKOVF bit 7 Legend:
PCON: POWER CONTROL REGISTER
U-0 -- U-0 -- R/W/HC-1/q RMCLR R/W/HC-1/q RI R/W/HC-q/u POR R/W/HC-q/u BOR bit 0 STKUNF
R/W/HS-0/q
HC = Bit is cleared by hardware R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared
HS = Bit is set by hardware U = Unimplemented bit, read as `0' -m/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition
STKOVF: Stack Overflow Flag bit 1 = A Stack Overflow occurred 0 = A Stack Overflow has not occurred or set to `0' by firmware STKUNF: Stack Underflow Flag bit 1 = A Stack Underflow occurred 0 = A Stack Underflow has not occurred or set to `0' by firmware Unimplemented: Read as `0' RMCLR: MCLR Reset Flag bit 1 = A MCLR Reset has not occurred or set to `1' by firmware 0 = A MCLR Reset has occurred (set to `0' in hardware when a MCLR Reset occurs) RI: RESET Instruction Flag bit 1 = A RESET instruction has not been executed or set to `1' by firmware 0 = A RESET instruction has been executed (set to `0' in hardware upon executing a RESET instruction) POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs)
bit 6
bit 5-4 bit 3
bit 2
bit 1
bit 0
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TABLE 7-5:
Name BORCON PCON STATUS WDTCON
SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Bit 7 Bit 6 -- STKUNF -- -- Bit 5 -- -- -- WDTPS4 Bit 4 -- -- TO WDTPS3 Bit 3 -- RMCLR PD WDTPS2 Bit 2 -- RI Z WDTPS1 Bit 1 -- POR DC Bit 0 BORRDY BOR C Register on Page 79 83 23 105
SBOREN STKOVF -- --
WDTPS0 SWDTEN
Legend: -- = unimplemented bit, reads as `0'. Shaded cells are not used by Resets. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
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8.0 INTERRUPTS
The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: * * * * * Operation Interrupt Latency Interrupts During Sleep INT Pin Automatic Context Saving
Many peripherals produce Interrupts. Refer to the corresponding chapters for details. A block diagram of the interrupt logic is shown in Figure 8-1 and Figure 8-2.
FIGURE 8-1:
INTERRUPT LOGIC
Wake-up (If in Sleep mode) TMR0IF TMR0IE INTF INTE IOCIF IOCIE From Peripheral Interrupt Logic (Figure 8-2) PEIE Interrupt to CPU
GIE
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FIGURE 8-2:
TMR1GIF TMR1GIE ADIF ADIE RCIF RCIE TXIF TXIE SSP1IF SSP1IE CCP1IF CCP1IE TMR2IF TMR2IE TMR1IF TMR1IE OSFIF OSFIE C2IF C2IE C1IF C1IE EEIF EEIE BCL1IF BCL1IE CCP2IF(1) CCP2IE(1) CCP4IF(1) CCP4IE(1) CCP3IF(1) CCP3IE(1) TMR6IF(1) TMR6IE(1) TMR4IF(1) TMR4IE(1) BCL2IF(1) BCL2IE(1) SSP2IF(1) SSP2IE(1)
PERIPHERAL INTERRUPT LOGIC -
To Interrupt Logic (Figure 5-1)
Note 1: These interrupts are available on PIC16F/LF1827 only
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8.1 Operation 8.2 Interrupt Latency
Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: * GIE bit of the INTCON register * Interrupt Enable bit(s) for the specific interrupt event(s) * PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIEx register) The INTCON, PIR1, PIR2, PIR3 and PIR4 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits. The following events happen when an interrupt event occurs while the GIE bit is set: * Current prefetched instruction is flushed * GIE bit is cleared * Current Program Counter (PC) is pushed onto the stack * Critical registers are automatically saved to the shadow registers (See Section 8.5 "Automatic Context Saving") * PC is loaded with the interrupt vector 0004h The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit. For additional information on a specific interrupt's operation, refer to its peripheral chapter. Note 1: Individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous interrupts is 3 or 4 instruction cycles. For asynchronous interrupts, the latency is 3 to 5 instruction cycles, depending on when the interrupt occurs. See Figure 8-3 and Figure 8.3 for more details.
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FIGURE 8-3:
OSC1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
INTERRUPT LATENCY
CLKOUT
Interrupt Sampled during Q1
Interrupt GIE
PC Execute
PC-1
PC Inst(PC)
PC+1 NOP
0004h NOP
0005h Inst(0004h)
1 Cycle Instruction at PC
Interrupt GIE PC+1/FSR ADDR Inst(PC) New PC/ PC+1 NOP
PC Execute
PC-1
PC
0004h NOP
0005h Inst(0004h)
2 Cycle Instruction at PC
Interrupt GIE
PC Execute
PC-1
PC
FSR ADDR INST(PC)
PC+1 NOP
PC+2 NOP
0004h NOP
0005h Inst(0004h) Inst(0005h)
3 Cycle Instruction at PC
Interrupt GIE
PC Execute
PC-1
PC
FSR ADDR INST(PC)
PC+1 NOP NOP
PC+2 NOP
0004h NOP
0005h Inst(0004h)
3 Cycle Instruction at PC
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FIGURE 8-4:
Q1 OSC1 CLKOUT (3) INT pin INTF GIE
(1) (5)
INT PIN INTERRUPT TIMING
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
(4) (1)
Interrupt Latency (2)
INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: 5:
PC
PC + 1 Inst (PC + 1) Inst (PC)
PC + 1 -- Dummy Cycle
0004h Inst (0004h) Dummy Cycle
0005h Inst (0005h) Inst (0004h)
Inst (PC) Inst (PC - 1)
INTF flag is sampled here (every Q1). Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. CLKOUT not available in all oscillator modes. For minimum width of INT pulse, refer to AC specifications in Section 29.0 "Electrical Specifications". INTF is enabled to be set any time during the Q4-Q1 cycles.
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8.3 Interrupts During Sleep
Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to the Section 9.0 "PowerDown Mode (Sleep)" for more details.
8.4
INT Pin
The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting the INTE bit of the INTCON register. The INTEDG bit of the OPTION register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector.
8.5
Automatic Context Saving
Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the Shadow registers: * * * * * W register STATUS register (except for TO and PD) BSR register FSR registers PCLATH register
Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding Shadow register should be modified and the value will be restored when exiting the ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the user's application, other registers may also need to be saved.
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8.5.1 INTCON REGISTER
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, interrupt-on-change and external INT pin interrupts.
REGISTER 8-1:
R/W-0/0 GIE bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7
INTCON: INTERRUPT CONTROL REGISTER
R/W-0/0 PEIE R/W-0/0 TMR0IE R/W-0/0 INTE R/W-0/0 IOCIE R/W-0/0 TMR0IF R/W-0/0 INTF R-0/0 IOCIF(1) bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
GIE: Global Interrupt Enable bit 1 = Enables all active interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all active peripheral interrupts 0 = Disables all peripheral interrupts TMR0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt INTE: INT External Interrupt Enable bit 1 = Enables the INT external interrupt 0 = Disables the INT external interrupt IOCIE: Interrupt-on-Change Enable bit 1 = Enables the interrupt-on-change 0 = Disables the interrupt-on-change TMR0IF: Timer0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed 0 = TMR0 register did not overflow INTF: INT External Interrupt Flag bit 1 = The INT external interrupt occurred 0 = The INT external interrupt did not occur IOCIF: Interrupt-on-Change Interrupt Flag bit(1) 1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state The IOCIF Flag bit is read only and cleared when all the interrupt-on-change flags in the IOCBF register have been cleared by software.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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8.5.2 PIE1 REGISTER
Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. The PIE1 register contains the interrupt enable bits, as shown in Register 8-2.
REGISTER 8-2:
R/W-0/0 TMR1GIE bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0/0 ADIE R/W-0/0 RCIE R/W-0/0 TXIE R/W-0/0 SSP1IE R/W-0/0 CCP1IE R/W-0/0 TMR2IE R/W-0/0 TMR1IE bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1 Gate Acquisition interrupt 0 = Disables the Timer1 Gate Acquisition interrupt ADIE: A/D Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt SSP1IE: Synchronous Serial Port 1 (MSSP1) Interrupt Enable bit 1 = Enables the MSSP1 interrupt 0 = Disables the MSSP1 interrupt CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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8.5.3 PIE2 REGISTER
Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. The PIE2 register contains the interrupt enable bits, as shown in Register 8-3.
REGISTER 8-3:
R/W-0/0 OSFIE bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0/0 C2IE R/W-0/0 C1IE R/W-0/0 EEIE R/W-0/0 BCL1IE U-0 -- U-0 -- R/W-0/0 CCP2IE(1) bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the Oscillator Fail interrupt 0 = Disables the Oscillator Fail interrupt C2IE: Comparator C2 Interrupt Enable bit 1 = Enables the Comparator C2 interrupt 0 = Disables the Comparator C2 interrupt C1IE: Comparator C1 Interrupt Enable bit 1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt EEIE: EEPROM Write Completion Interrupt Enable bit 1 = Enables the EEPROM Write Completion interrupt 0 = Disables the EEPROM Write Completion interrupt BCL1IE: MSSP1 Bus Collision Interrupt Enable bit 1 = Enables the MSSP1 Bus Collision Interrupt 0 = Disables the MSSP1 Bus Collision Interrupt Unimplemented: Read as `0' CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt PIC16F/LF1827 only.
bit 6
bit 5
bit 4
bit 3
bit 2-1 bit 0
Note 1:
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8.5.4 PIE3 REGISTER(1)
Note 1: The PIE3 register is available only on the PIC16F/LF1827 device. 2: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. The PIE3 register contains the interrupt enable bits, as shown in Register 8-4.
REGISTER 8-4:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6 bit 5
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3(1)
U-0 -- R/W-0/0 CCP4IE R/W-0/0 CCP3IE R/W-0/0 TMR6IE U-0 -- R/W-0/0 TMR4IE U-0 -- bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
Unimplemented: Read as `0' CCP4IE: CCP4 Interrupt Enable bit 1 = Enables the CCP4 interrupt 0 = Disables the CCP4 interrupt CCP3IE: CCP3 Interrupt Enable bit 1 = Enables the CCP3 interrupt 0 = Disables the CCP3 interrupt TMR6IE: TMR6 to PR6 Match Interrupt Enable bit 1 = Enables the TMR6 to PR6 Match interrupt 0 = Disables the TMR6 to PR6 Match interrupt Unimplemented: Read as `0' TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enables the TMR4 to PR4 Match interrupt 0 = Disables the TMR4 to PR4 Match interrupt Unimplemented: Read as `0' This register is only available on PIC16F/LF1827.
bit 4
bit 3
bit 2 bit 1
bit 0 Note 1:
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8.5.5 PIE4 REGISTER(1)
Note 1: The PIE4 register is available only on the PIC16F/LF1827 device. 2: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. The PIE4 register contains the interrupt enable bits, as shown in Register 8-5.
REGISTER 8-5:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-2 bit 1
PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4(1)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0/0 BCL2IE R/W-0/0 SSP2IE bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
Unimplemented: Read as `0' BCL2IE: MSSP2 Bus Collision Interrupt Enable bit 1 = Enables the MSSP2 Bus Collision Interrupt 0 = Disables the MSSP2 Bus Collision Interrupt SSP2IE: Master Synchronous Serial Port 2 (MSSP2) Interrupt Enable bit 1 = Enables the MSSP2 interrupt 0 = Disables the MSSP2 interrupt This register is only available on PIC16F/LF1827.
bit 0
Note 1:
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8.5.6 PIR1 REGISTER
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The PIR1 register contains the interrupt flag bits, as shown in Register 8-6.
REGISTER 8-6:
R/W-0/0 TMR1GIF bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0/0 ADIF R-0/0 RCIF R-0/0 TXIF R/W-0/0 SSP1IF R/W-0/0 CCP1IF R/W-0/0 TMR2IF R/W-0/0 TMR1IF bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending ADIF: A/D Converter Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending RCIF: USART Receive Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending TXIF: USART Transmit Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending SSP1IF: Synchronous Serial Port 1 (MSSP1) Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending CCP1IF: CCP1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending TMR2IF: Timer2 to PR2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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8.5.7 PIR2 REGISTER
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The PIR2 register contains the interrupt flag bits, as shown in Register 8-7.
REGISTER 8-7:
R/W-0/0 OSFIF bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0/0 C2IF R/W-0/0 C1IF R/W-0/0 EEIF R/W-0/0 BCL1IF U-0 -- U-0 -- R/W-0/0 CCP2IF(1) bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
OSFIF: Oscillator Fail Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending C2IF: Comparator C2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending C1IF: Comparator C1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending EEIF: EEPROM Write Completion Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending BCL1IF: MSSP1 Bus Collision Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Unimplemented: Read as `0' CCP2IF: CCP2 Interrupt Flag bit(1) 1 = Interrupt is pending 0 = Interrupt is not pending PIC16F/LF1827 only.
bit 6
bit 5
bit 4
bit 3
bit 2-1 bit 0
Note 1:
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8.5.8 PIR3 REGISTER(1)
Note 1: The PIR3 register is available only on the PIC16F/LF1827 device. 2: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The PIR3 register contains the interrupt flag bits, as shown in Register 8-8.
REGISTER 8-8:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6 bit 5
PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3(1)
U-0 -- R/W-0/0 CCP4IF R/W-0/0 CCP3IF R/W-0/0 TMR6IF U-0 -- R/W-0/0 TMR4IF U-0 -- bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
Unimplemented: Read as `0' CCP4IF: CCP4 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending CCP3IF: CCP3 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending TMR6IF: TMR6 to PR6 Match Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Unimplemented: Read as `0' TMR4IF: TMR4 to PR4 Match Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Unimplemented: Read as `0' This register is only available on PIC16F/LF1827.
bit 4
bit 3
bit 2 bit 1
bit 0 Note 1:
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8.5.9 PIR4 REGISTER(1)
Note 1: The PIR4 register is available only on the PIC16F/LF1827 device. 2: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The PIR4 register contains the interrupt flag bits, as shown in Register 8-9.
REGISTER 8-9:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-2 bit 1
PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4(1)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W/HS-0/0 BCL2IF R/W/HS-0/0 SSP2IF bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets HS = Bit is set by hardware
Unimplemented: Read as `0' BCL2IF: MSSP2 Bus Collision Interrupt Flag bit 1 = A Bus Collision was detected (must be cleared in software) 0 = No Bus collision was detected SSP2IF: Master Synchronous Serial Port 2 (MSSP2) Interrupt Flag bit 1 = The Transmission/Reception/Bus Condition is complete (must be cleared in software) 0 = Waiting to Transmit/Receive/Bus Condition in progress This register is only available on PIC16F/LF1827.
bit 0
Note 1:
TABLE 8-1:
Name INTCON OPTION_REG PIE1 PIE2 PIE3
(1)
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Bit 7 GIE WPUEN TMR1GIE OSFIE -- -- TMR1GIF OSFIF -- -- Bit 6 PEIE INTEDG ADIE C2IE -- -- ADIF C2IF -- -- Bit 5 TMR0IE TMR0CS RCIE C1IE CCP4IE -- RCIF C1IF CCP4IF -- Bit 4 INTE TMR0SE TXIE EEIE CCP3IE -- TXIF EEIF CCP3IF -- Bit 3 IOCIE PSA SSP1IE BCL1IE TMR6IE -- SSP1IF BCL1IF TMR6IF -- Bit 2 TMR0IF PS2 CCP1IE -- -- -- CCP1IF -- -- -- Bit 1 INTF PS1 TMR2IE -- TMR4IE BCL2IE TMR2IF -- TMR4IF BCL2IF Bit 0 IOCIF PS0 TMR1IE CCP2IE(1) -- SSP2IE TMR1IF CCP2IF(1) -- SSP2IF Register on Page 91 177 92 93 94 95 96 97 98 99
PIE4(1) PIR1 PIR2 PIR3(1) PIR4(1) Legend: Note 1:
-- = unimplemented locations read as `0'. Shaded cells are not used by Interrupts. PIC16F/LF1827 only.
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9.0 POWER-DOWN MODE (SLEEP)
9.1 Wake-up from Sleep
The Power-Down mode is entered by executing a SLEEP instruction. Upon entering Sleep mode, the following conditions exist: WDT will be cleared but keeps running, if enabled for operation during Sleep. 2. PD bit of the STATUS register is cleared. 3. TO bit of the STATUS register is set. 4. CPU clock is disabled. 5. 31 kHz LFINTOSC is unaffected and peripherals that operate from it may continue operation in Sleep. 6. Timer1 oscillator is unaffected and peripherals that operate from it may continue operation in Sleep. 7. ADC is unaffected, if the dedicated FRC clock is selected. 8. Capacitive Sensing oscillator is unaffected. 9. I/O ports maintain the status they had before SLEEP was executed (driving high, low or highimpedance). 10. Resets other than WDT are not affected by Sleep mode. Refer to individual chapters for more details on peripheral operation during Sleep. To minimize current consumption, the following conditions should be considered: * * * * * * I/O pins should not be floating External circuitry sinking current from I/O pins Internal circuitry sourcing current from I/O pins Current draw from pins with internal weak pull-ups Modules using 31 kHz LFINTOSC Modules using Timer1 oscillator 1. The device can wake-up from Sleep through one of the following events: 1. 2. 3. 4. 5. 6. External Reset input on MCLR pin, if enabled BOR Reset, if enabled POR Reset Watchdog Timer, if enabled Any external interrupt Interrupts by peripherals capable of running during Sleep (see individual peripheral for more information)
The first three events will cause a device Reset. The last three events are considered a continuation of program execution. To determine whether a device Reset or wake-up event occurred, refer to Section 7.10 "Determining the Cause of a Reset". When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up will occur regardless of the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is enabled, the device executes the instruction after the SLEEP instruction, the device will call the Interrupt Service Routine. In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up.
I/O pins that are high-impedance inputs should be pulled to VDD or VSS externally to avoid switching currents caused by floating inputs. Examples of internal circuitry that might be sourcing current include modules such as the DAC and FVR modules. See Section 16.0 "Digital-to-Analog Converter (DAC) Module" and Section 14.0 "Fixed Voltage Reference (FVR)" for more information on these modules.
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9.1.1 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP. - WDT and WDT prescaler will not be cleared - TO bit of the STATUS register will not be set - PD bit of the STATUS register will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction - SLEEP instruction will be completely executed - Device will immediately wake-up from Sleep - WDT and WDT prescaler will be cleared - TO bit of the STATUS register will be set - PD bit of the STATUS register will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP.
FIGURE 9-1:
OSC1(1) CLKOUT(2) Interrupt flag GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 TOST(3) Interrupt Latency (4) Processor in Sleep
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
PC Inst(PC) = Sleep Inst(PC - 1)
PC + 1 Inst(PC + 1) Sleep
PC + 2
PC + 2 Inst(PC + 2) Inst(PC + 1)
PC + 2
0004h Inst(0004h)
0005h Inst(0005h) Inst(0004h)
Dummy Cycle
Dummy Cycle
XT, HS or LP Oscillator mode assumed. CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference. TOST = 1024 TOSC (drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes. GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
TABLE 9-1:
Name INTCON IOCBF IOCBN IOCBP PIE1 PIE2 PIE4(1) PIR1 PIR2 PIR4(1) STATUS WDTCON Legend: Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Bit 7 GIE IOCBF7 IOCBN7 IOCBP7 Bit 6 PEIE IOCBF6 IOCBN6 IOCBP6 ADIE C2IE -- ADIF C2IF -- -- -- Bit 5 TMR0IE IOCBF5 IOCBN5 IOCBP5 RCIE C1IE -- RCIF C1IF -- -- WDTPS4 Bit 4 INTE IOCBF4 IOCBN4 IOCBP4 TXIE EEIE -- TXIF EEIF -- TO WDTPS3 Bit 3 IOCIE IOCBF3 IOCBN3 IOCBP3 SSP1IE BCL1IE -- SSP1IF BCL1IF -- PD WDTPS2 Bit 2 TMR0IF IOCBF2 IOCBN2 IOCBP2 CCP1IE -- -- CCP1IF -- -- Z WDTPS1 Bit 1 INTF IOCBF1 IOCBN1 IOCBP1 TMR2IE -- BCL2IE TMR2IF -- BCL2IF DC WDTPS0 Bit 0 IOCIF IOCBF0 IOCBN0 IOCBP0 TMR1IE CCP2IE(1) SSP2IE TMR1IF CCP2IF(1) SSP2IF C SWDTEN Register on Page 91 134 134 134 92 93 95 96 97 99 23 105
TMR1GIE OSFIE -- TMR1GIF OSFIF -- -- --
-- = unimplemented, read as `0'. Shaded cells are not used in Power-down mode. PIC16F/LF1827 only.
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10.0 WATCHDOG TIMER
The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events. The WDT has the following features: * Independent clock source * Multiple operating modes - WDT is always on - WDT is off when in Sleep - WDT is controlled by software - WDT is always off * Configurable time-out period is from 1 ms to 256 seconds (typical) * Multiple Reset conditions * Operation during Sleep
FIGURE 10-1:
WDTE<1:0> = 01 SWDTEN WDTE<1:0> = 11 WDTE<1:0> = 10 Sleep
WATCHDOG TIMER BLOCK DIAGRAM
LFINTOSC
23-bit Programmable Prescaler WDT
WDT Time-out
WDTPS<4:0>
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10.1 Independent Clock Source 10.3 Time-Out Period
The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. The WDTPS bits of the WDTCON register set the time-out period from 1 ms to 256 seconds. After a Reset, the default time-out period is 2 seconds.
10.2
WDT Operating Modes
The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration Word 1. See Table 10-1.
10.4
Clearing the WDT
The WDT is cleared when any of the following conditions occur: * * * * * * * Any Reset CLRWDT instruction is executed Device enters Sleep Device wakes up from Sleep Oscillator fail event WDT is disabled Oscillator Start-up TImer (OST) is running
10.2.1
WDT IS ALWAYS ON
When the WDTE bits of Configuration Word 1 are set to `11', the WDT is always on. WDT protection is active during Sleep.
10.2.2
WDT IS OFF IN SLEEP
When the WDTE bits of Configuration Word 1 are set to `10', the WDT is on, except in Sleep. WDT protection is not active during Sleep.
See Table 10-2 for more information.
10.5
Operation During Sleep
10.2.3
WDT CONTROLLED BY SOFTWARE
When the WDTE bits of Configuration Word 1 are set to `01', the WDT is controlled by the SWDTEN bit of the WDTCON register. WDT protection is unchanged Table 10-1 for more details. by Sleep. See
When the device enters Sleep, the WDT is cleared. If the WDT is enabled during Sleep, the WDT resumes counting. When the device exits Sleep, the WDT is cleared again. The WDT remains clear until the OST, if enabled, completes. See Section 5.0 "Oscillator Module (With Fail-Safe Clock Monitor)" for more information on the OST. When a WDT time-out occurs while the device is in Sleep, no Reset is generated. Instead, the device wakes up and resumes operation. The TO and PD bits in the STATUS register are changed to indicate the event. See Section 3.0 "Memory Organization" for more information.
TABLE 10-1:
WDTE Config bits WDT_ON (11)
WDT OPERATING MODES
SWDTEN X X X 1 0 X Device Mode X Awake Sleep X X X WDT Mode Active Active Disabled Active Disabled Disabled
WDT_NSLEEP (10) WDT_NSLEEP (10) WDT_SWDTEN (01) WDT_SWDTEN (01) WDT_OFF (00)
TABLE 10-2:
WDT CLEARING CONDITIONS
Conditions WDT
WDTE<1:0> = 00 WDTE<1:0> = 01 and SWDTEN = 0 WDTE<1:0> = 10 and enter Sleep CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Change INTOSC divider (IRCF bits) Cleared until the end of OST Unaffected Cleared
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REGISTER 10-1:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6 bit 5-1 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0' WDTPS<4:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 00000 = 1:32 (Interval 1 ms typ) 00001 = 1:64 (Interval 2 ms typ) 00010 = 1:128 (Interval 4 ms typ) 00011 = 1:256 (Interval 8 ms typ) 00100 = 1:512 (Interval 16 ms typ) 00101 = 1:1024 (Interval 32 ms typ) 00110 = 1:2048 (Interval 64 ms typ) 00111 = 1:4096 (Interval 128 ms typ) 01000 = 1:8192 (Interval 256 ms typ) 01001 = 1:16384 (Interval 512 ms typ) 01010 = 1:32768 (Interval 1s typ) 01011 = 1:65536 (Interval 2s typ) (Reset value) 01100 = 1:131072 (217) (Interval 4s typ) 01101 = 1:262144 (218) (Interval 8s typ) 01110 = 1:524288 (219) (Interval 16s typ) 01111 = 1:1048576 (220) (Interval 32s typ) 10000 = 1:2097152 (221) (Interval 64s typ) 10001 = 1:4194304 (222) (Interval 128s typ) 10010 = 1:8388608 (223) (Interval 256s typ) 10011 = Reserved. Results in minimum interval (1:32) * * * 11111 = Reserved. Results in minimum interval (1:32) bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 00: This bit is ignored. If WDTE<1:0> = 01: 1 = WDT is turned on 0 = WDT is turned off If WDTE<1:0> = 1x: This bit is ignored. U = Unimplemented bit, read as `0' -m/n = Value at POR and BOR/Value at all other Resets
WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0 -- R/W-0/0 R/W-1/1 R/W-0/0 WDTPS<4:0> R/W-1/1 R/W-1/1 R/W-0/0 SWDTEN bit 0
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11.0 DATA EEPROM AND FLASH PROGRAM MEMORY CONTROL
11.1 EEADRL and EEADRH Registers
The EEADRH:EEADRL register pair can address up to a maximum of 256 bytes of data EEPROM or up to a maximum of 32K words of program memory. When selecting a program address value, the MSB of the address is written to the EEADRH register and the LSB is written to the EEADRL register. When selecting a EEPROM address value, only the LSB of the address is written to the EEADRL register.
The Data EEPROM and Flash program memory are readable and writable during normal operation (full VDD range). These memories are not directly mapped in the register file space. Instead, they are indirectly addressed through the Special Function Registers (SFRs). There are six SFRs used to access these memories: * * * * * * EECON1 EECON2 EEDATL EEDATH EEADRL EEADRH
11.1.1
EECON1 AND EECON2 REGISTERS
EECON1 is the control register for EE memory accesses. Control bit EEPGD determines if the access will be a program or data memory access. When clear, any subsequent operations will operate on the EEPROM memory. When set, any subsequent operations will operate on the program memory. On Reset, EEPROM is selected by default. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write operation to occur. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit and execute the appropriate error handling routine. Interrupt flag bit EEIF of the PIR2 register is set when write is complete. It must be cleared in the software. Reading EECON2 will read all `0's. The EECON2 register is used exclusively in the data EEPROM write sequence. To enable writes, a specific pattern must be written to EECON2.
When interfacing the data memory block, EEDATL holds the 8-bit data for read/write, and EEADRL holds the address of the EEDATL location being accessed. These devices have 256 bytes of data EEPROM with an address range from 0h to 0FFh. When accessing the program memory block, the EEDATH:EEDATL register pair forms a 2-byte word that holds the 14-bit data for read/write, and the EEADRL and EEADRH registers form a 2-byte word that holds the 15-bit address of the program memory location being read. The EEPROM data memory allows byte read and write. An EEPROM byte write automatically erases the location and writes the new data (erase before write). The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations. Depending on the setting of the Flash Program Memory Self Write Enable bits WRT<1:0> of the Configuration Word 2, the device may or may not be able to write certain blocks of the program memory. However, reads from the program memory are always allowed. When the device is code-protected, the device programmer can no longer access data or program memory. When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory.
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11.2 Using the Data EEPROM
11.2.2
The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). When variables in one section change frequently, while variables in another section do not change, it is possible to exceed the total number of write cycles to the EEPROM without exceeding the total number of write cycles to a single byte. Refer to Section 29.0 "Electrical Specifications". If this is the case, then a refresh of the array must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory.
WRITING TO THE DATA EEPROM MEMORY
To write an EEPROM data location, the user must first write the address to the EEADRL register and the data to the EEDATL register. Then the user must follow a specific sequence to initiate the write for each byte. The write will not initiate if the above sequence is not followed exactly (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. Interrupts should be disabled during this code segment. Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware. After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software.
11.2.1
READING THE DATA EEPROM MEMORY
To read a data memory location, the user must write the address to the EEADRL register, clear the EEPGD and CFGS control bits of the EECON1 register, and then set control bit RD. The data is available at the very next cycle, in the EEDATL register; therefore, it can be read in the next instruction. EEDATL will hold this value until another read or until it is written to by the user (during a write operation).
EXAMPLE 11-1:
DATA EEPROM READ
11.2.3
BANKSEL EEADRL ; MOVLW DATA_EE_ADDR ; MOVWF EEADRL ;Data Memory ;Address to read BCF EECON1, CFGS ;Deselect Config space BCF EECON1, EEPGD;Point to DATA memory BSF EECON1, RD ;EE Read MOVF EEDATL, W ;W = EEDATL
PROTECTION AGAINST SPURIOUS WRITE
There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up, WREN is cleared. Also, the Power-up Timer (64 ms duration) prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during: * Brown-out * Power Glitch * Software Malfunction
Note:
Data EEPROM can be read regardless of the setting of the CPD bit.
11.2.4
DATA EEPROM OPERATION DURING CODE-PROTECT
Data memory can be code-protected by programming the CPD bit in the Configuration Word 1 (Register 5-1) to `0'. When the data memory is code-protected, only the CPU is able to read and write data to the data EEPROM. It is recommended to code-protect the program memory when code-protecting data memory. This prevents anyone from replacing your program with a program that will access the contents of the data EEPROM.
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EXAMPLE 11-2:
BANKSEL MOVLW MOVWF MOVLW MOVWF BCF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF BTFSC GOTO
DATA EEPROM WRITE
EEADRL DATA_EE_ADDR EEADRL DATA_EE_DATA EEDATL EECON1, CFGS EECON1, EEPGD EECON1, WREN INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, EECON1, EECON1, $-2 GIE ; ; ;Data Memory Address to write ; ;Data Memory Value to write ;Deselect Configuration space ;Point to DATA memory ;Enable writes ;Disable INTs. ; ;Write 55h ; ;Write AAh ;Set WR bit to begin write ;Enable Interrupts ;Disable writes ;Wait for write to complete ;Done
Required Sequence
WR GIE WREN WR
FIGURE 11-1:
FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Flash ADDR
PC
PC + 1
EEADRH,EEADRL
PC + 3 PC+3
PC + 4
PC + 5
Flash Data
INSTR (PC)
INSTR (PC + 1)
EEDATH,EEDATL
INSTR (PC + 3)
INSTR (PC + 4)
INSTR(PC - 1) executed here
BSF EECON1,RD executed here
INSTR(PC + 1) executed here
Forced NOP executed here
INSTR(PC + 3) executed here
INSTR(PC + 4) executed here
RD bit
EEDATH EEDATL Register
EERHLT
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11.3 Flash Program Memory Overview
11.3.1
It is important to understand the Flash program memory structure for erase and programming operations. Flash Program memory is arranged in rows. A row consists of a fixed number of 14-bit program memory words. A row is the minimum block size that can be erased by user software. Flash program memory may only be written or erased if the destination address is in a segment of memory that is not write-protected, as defined in bits WRT<1:0> of Configuration Word 2. After a row has been erased, the user can reprogram all or a portion of this row. Data to be written into the program memory row is written to 14-bit wide data write latches. These write latches are not directly accessible to the user, but may be loaded via sequential writes to the EEDATH:EEDATL register pair. Note: If the user wants to modify only a portion of a previously programmed row, then the contents of the entire row must be read and saved in RAM prior to the erase.
READING THE FLASH PROGRAM MEMORY
To read a program memory location, the user must: 1. 2. 3. 4. Write the Least and Most Significant address bits to the EEADRH:EEADRL register pair. Clear the CFGS bit of the EECON1 register. Set the EEPGD control bit of the EECON1 register. Then, set control bit RD of the EECON1 register.
Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the "BSF EECON1,RD" instruction to be ignored. The data is available in the very next cycle, in the EEDATH:EEDATL register pair; therefore, it can be read as two bytes in the following instructions. EEDATH:EEDATL register pair will hold this value until another read or until it is written to by the user. Note 1: The two instructions following a program memory read are required to be NOPs. This prevents the user from executing a two-cycle instruction on the next instruction after the RD bit is set. 2: Flash program memory can be read regardless of the setting of the CP bit.
The number of data write latches is not equivalent to the number of row locations. During programming, user software will need to fill the set of write latches and initiate a programming operation multiple times in order to fully reprogram an erased row. For example, a device with a row size of 32 words and eight write latches will need to load the write latches with data and initiate a programming operation four times. The size of a program memory row and the number of program memory write latches may vary by device. See Table 11-1 for details.
TABLE 11-1:
FLASH MEMORY ORGANIZATION BY DEVICE
Erase Block (Row) Size/ Boundary 32 words, EEADRL<4:0 > = 00000 Number of Write Latches/ Boundary 32 words, EEADRL<4:0> = 00000
Device PIC16F/LF1826/27
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EXAMPLE 11-3: FLASH PROGRAM MEMORY READ
* This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI : PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF MOVLW MOVWL BCF BSF BCF BSF NOP NOP BSF MOVF MOVWF MOVF MOVWF EEADRL PROG_ADDR_LO EEADRL PROG_ADDR_HI EEADRH EECON1,CFGS EECON1,EEPGD INTCON,GIE EECON1,RD ; Select Bank for EEPROM registers ; ; Store LSB of address ; ; Store MSB of address ; ; ; ; ; ; ; ; ; ; ; Do not select Configuration Space Select Program Memory Disable interrupts Initiate read Executed (Figure 11-1) Ignored (Figure 11-1) Restore interrupts Get LSB of word Store in user location Get MSB of word Store in user location
INTCON,GIE EEDATL,W PROG_DATA_LO EEDATH,W PROG_DATA_HI
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11.3.2 ERASING FLASH PROGRAM MEMORY
While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. 6. Load the EEADRH:EEADRL register pair with the address of new row to be erased. Clear the CFGS bit of the EECON1 register. Set the EEPGD, FREE, and WREN bits of the EECON1 register. Write 55h, then AAh, to EECON2 (Flash programming unlock sequence). Set control bit WR of the EECON1 register to begin the erase operation. Poll the FREE bit in the EECON1 register to determine when the row erase has completed. The following steps should be completed to load the write latches and program a block of program memory. These steps are divided into two parts. First, all write latches are loaded with data except for the last program memory location. Then, the last write latch is loaded and the programming sequence is initiated. A special unlock sequence is required to load a write latch with data or initiate a Flash programming operation. This unlock sequence should not be interrupted. Set the EEPGD and WREN bits of the EECON1 register. 2. Clear the CFGS bit of the EECON1 register. 3. Set the LWLO bit of the EECON1 register. When the LWLO bit of the EECON1 register is `1', the write sequence will only load the write latches and will not initiate the write to Flash program memory. 4. Load the EEADRH:EEADRL register pair with the address of the location to be written. 5. Load the EEDATH:EEDATL register pair with the program memory data to be written. 6. Write 55h, then AAh, to EECON2, then set the WR bit of the EECON1 register (Flash programming unlock sequence). The write latch is now loaded. 7. Increment the EEADRH:EEADRL register pair to point to the next location. 8. Repeat steps 5 through 7 until all but the last write latch has been loaded. 9. Clear the LWLO bit of the EECON1 register. When the LWLO bit of the EECON1 register is `0', the write sequence will initiate the write to Flash program memory. 10. Load the EEDATH:EEDATL register pair with the program memory data to be written. 11. Write 55h, then AAh, to EECON2, then set the WR bit of the EECON1 register (Flash programming unlock sequence). The entire latch block is now written to Flash program memory. It is not necessary to load the entire write latch block with user program data. However, the entire write latch block will be written to program memory. An example of the complete write sequence for eight words is shown in Example 11-5. The initial address is loaded into the EEADRH:EEADRL register pair; the eight words of data are loaded using indirect addressing. Note: If the number of write latches is smaller than the erase block size, the code sequence provided in Example 11-5 must be repeated multiple times to fully program an erased program memory row. 1.
See Example 11-4. After the "BSF EECON1,WR" instruction, the processor requires two cycles to set up the erase operation. The user must place two NOP instructions after the WR bit is set. The processor will halt internal operations for the typical 2 ms erase time. This is not Sleep mode as the clocks and peripherals will continue to run. After the erase cycle, the processor will resume operation with the third instruction after the EECON1 write instruction.
11.3.3
WRITING TO FLASH PROGRAM MEMORY
Program memory is programmed using the following steps: 1. 2. 3. 4. Load the starting address of the word(s) to be programmed. Load the write latches with data. Initiate a programming operation. Repeat steps 1 through 3 until all data is written.
Before writing to program memory, the word(s) to be written must be erased or previously unwritten. Program memory can only be erased one row at a time. No automatic erase occurs upon the initiation of the write. Program memory can be written one or more words at a time. The maximum number of words written at one time is equal to the number of write latches. See Figure 11-2 (block writes to program memory with 32 write latches) for more details. The write latches are aligned to the address boundary defined by EEADRL as shown in Table 11-1. Write operations do not cross these boundaries. At the completion of a program memory write operation, the write latches are reset to contain 0x3FFF.
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After the "BSF EECON1,WR" instruction, the processor requires two cycles to set up the write operation. The user must place two NOP instructions after the WR bit is set. The processor will halt internal operations for the typical 2 ms, only during the cycle in which the write takes place (i.e., the last word of the block write). This is not Sleep mode as the clocks and peripherals will continue to run. The processor does not stall when LWLO = 1, loading the write latches. After the write cycle, the processor will resume operation with the third instruction after the EECON1 write instruction.
FIGURE 11-2:
BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES
7 5 EEDATH 07 EEDATA 0
6
First word of block to be written
8
Last word of block to be written
14
EEADRL<4:0> = 00000 EEADRL<4:0> = 00001
14
EEADRL<4:0> = 00010
14
EEADRL<4:0> = 11111
14
Buffer Register
Buffer Register
Buffer Register
Buffer Register
Program Memory
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EXAMPLE 11-4: ERASING ONE ROW OF PROGRAM MEMORY ; This row erase routine assumes the following: ; 1. A valid address within the erase block is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F
BCF BANKSEL MOVF MOVWF MOVF MOVWF BSF BCF BSF BSF MOVLW MOVWF MOVLW MOVWF BSF NOP NOP
INTCON,GIE EEADRL ADDRL,W EEADRL ADDRH,W EEADRH EECON1,EEPGD EECON1,CFGS EECON1,FREE EECON1,WREN 55h EECON2 0AAh EECON2 EECON1,WR
; Disable ints so required sequences will execute properly ; Load lower 8 bits of erase address boundary ; Load upper 6 bits of erase address boundary ; ; ; ; ; ; ; ; ; ; ; ; Point to program memory Not configuration space Specify an erase operation Enable writes Start of required sequence to initiate erase Write 55h Write AAh Set WR bit to begin erase Any instructions here are ignored as processor halts to begin erase sequence Processor will stop here and wait for erase complete.
Required Sequence
; after erase processor continues with 3rd instruction BCF BSF EECON1,WREN INTCON,GIE ; Disable writes ; Enable interrupts
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EXAMPLE 11-5:
; ; ; ; ; ; ;
WRITING TO FLASH PROGRAM MEMORY
This write routine assumes the following: 1. The 16 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the least significant bits = 000) is loaded in ADDRH:ADDRL 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F BCF BANKSEL MOVF MOVWF MOVF MOVWF MOVLW MOVWF MOVLW MOVWF BSF BCF BSF BSF INTCON,GIE EEADRH ADDRH,W EEADRH ADDRL,W EEADRL LOW DATA_ADDR FSR0L HIGH DATA_ADDR FSR0H EECON1,EEPGD EECON1,CFGS EECON1,WREN EECON1,LWLO FSR0++ EEDATL FSR0++ EEDATH EEADRL,W 0x07 0x07 STATUS,Z START_WRITE 55h EECON2 0AAh EECON2 EECON1,WR ; ; ; ; ; ; ; ; ; ; ; ; ; ; Disable ints so required sequences will execute properly Bank 3 Load initial address
Load initial data address Load initial data address Point to program memory Not configuration space Enable writes Only Load Write Latches
LOOP MOVIW MOVWF MOVIW MOVWF MOVF XORLW ANDLW BTFSC GOTO MOVLW MOVWF MOVLW MOVWF BSF NOP NOP ; Load first data byte into lower ; ; Load second data byte into upper ; ; Check if lower bits of address are '000' ; Check if we're on the last of 8 addresses ; ; Exit if last of eight words, ; ; ; ; ; ; ; ; ; Start of required write sequence: Write 55h Write AAh Set WR bit to begin write Any instructions here are ignored as processor halts to begin write sequence Processor will stop here and wait for write to complete.
Required Sequence
; After write processor continues with 3rd instruction. INCF GOTO START_WRITE BCF EEADRL,F LOOP ; Still loading latches Increment address ; Write next latches
EECON1,LWLO
; No more loading latches - Actually start Flash program ; memory write ; ; ; ; ; ; ; ; Start of required write sequence: Write 55h Write AAh Set WR bit to begin write Any instructions here are ignored as processor halts to begin write sequence Processor will stop here and wait for write complete.
MOVLW MOVWF MOVLW MOVWF BSF NOP NOP
Required Sequence
55h EECON2 0AAh EECON2 EECON1,WR
BCF BSF
EECON1,WREN INTCON,GIE
; after write processor continues with 3rd instruction ; Disable writes ; Enable interrupts
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11.4 Modifying Flash Program Memory 11.5
When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. 8. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory. Load the starting address of the row to be rewritten. Erase the program memory row. Load the write latches with data from the RAM image. Initiate a programming operation. Repeat steps 6 and 7 as many times as required to reprogram the erased row.
User ID, Device ID and Configuration Word Access
Instead of accessing program memory or EEPROM data memory, the User ID's, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1 in the EECON1 register. This is the region that would be pointed to by PC<15> = 1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table 11-2. When read access is initiated on an address outside the parameters listed in Table 11-2, the EEDATH:EEDATL register pair is cleared.
TABLE 11-2:
USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)
Function User IDs Device ID/Revision ID Configuration Words 1 and 2 Read Access Yes Yes Yes Write Access Yes No No
Address 8000h-8003h 8006h 8007h-8008h
EXAMPLE 11-3:
CONFIGURATION WORD AND DEVICE ID ACCESS
* This code block will read 1 word of program memory at the memory address: * PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF CLRF BSF BCF BSF NOP NOP BSF MOVF MOVWF MOVF MOVWF EEADRL PROG_ADDR_LO EEADRL EEADRH EECON1,CFGS INTCON,GIE EECON1,RD ; Select correct Bank ; ; Store LSB of address ; Clear MSB of address ; ; ; ; ; ; ; ; ; ; Select Configuration Space Disable interrupts Initiate read Executed (See Figure 11-1) Ignored (See Figure 11-1) Restore interrupts Get LSB of word Store in user location Get MSB of word Store in user location
INTCON,GIE EEDATL,W PROG_DATA_LO EEDATH,W PROG_DATA_HI
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11.6 Write Verify
Depending on the application, good programming practice may dictate that the value written to the data EEPROM or program memory should be verified (see Example 11-6) to the desired value to be written. Example 11-6 shows how to verify a write to EEPROM.
EXAMPLE 11-6:
BANKSEL EEDATL MOVF EEDATL, W BSF XORWF BTFSS GOTO :
EEPROM WRITE VERIFY
; ;EEDATL not changed ;from previous write EECON1, RD ;YES, Read the ;value written EEDATL, W ; STATUS, Z ;Is data the same WRITE_ERR ;No, handle error ;Yes, continue
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REGISTER 11-1:
R/W-x/u bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared EEDAT<7:0>: Read/write value for EEPROM data byte or Least Significant bits of program memory U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
EEDATL: EEPROM DATA REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u bit 0 EEDAT<7:0>
REGISTER 11-2:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6 bit 5-0
EEDATH: EEPROM DATA HIGH BYTE REGISTER
U-0 -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u bit 0 EEDAT<13:8>
W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0'
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
EEDAT<13:8>: Read/write value for Most Significant bits of program memory
REGISTER 11-3:
R/W-0/0 bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-0
EEADRL: EEPROM ADDRESS REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 bit 0 EEADR<7:0>
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
EEADR<7:0>: Specifies the Least Significant bits for program memory address or EEPROM address
REGISTER 11-4:
U-1 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 bit 6-0
EEADRH: EEPROM ADDRESS HIGH BYTE REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 EEADR<14:8> bit 0 R/W-0/0 R/W-0/0 R/W-0/0
W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0'
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
EEADR<14:8>: Specifies the Most Significant bits for program memory address or EEPROM address
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REGISTER 11-5:
R/W-0/0 EEPGD bit 7 Legend: R = Readable bit S = Bit can only be set `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets HC = Bit is cleared by hardware
EECON1: EEPROM CONTROL 1 REGISTER
R/W-0/0 LWLO R/W/HC-0/0 FREE R/W-x/q WRERR R/W-0/0 WREN R/S/HC-0/0 WR R/S/HC-0/0 RD bit 0 CFGS
R/W-0/0
EEPGD: Flash Program/Data EEPROM Memory Select bit 1 = Accesses program space Flash memory 0 = Accesses data EEPROM memory CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Accesses Configuration, User ID and Device ID Registers 0 = Accesses Flash Program or data EEPROM Memory LWLO: Load Write Latches Only bit If CFGS = 1 (Configuration space) OR CFGS = 0 and EEPGD = 1 (program Flash): 1 = The next WR command does not initiate a write; only the program memory latches are updated. 0 = The next WR command writes a value from EEDATH:EEDATL into program memory latches and initiates a write of all the data stored in the program memory latches. If CFGS = 0 and EEPGD = 0: (Accessing data EEPROM) LWLO is ignored. The next WR command initiates a write to the data EEPROM.
bit 6
bit 5
bit 4
FREE: Program Flash Erase Enable bit If CFGS = 1 (Configuration space) OR CFGS = 0 and EEPGD = 1 (program Flash): 1 = Performs an erase operation on the next WR command (cleared by hardware after completion of erase). 0 = Performs a write operation on the next WR command. If EEPGD = 0 and CFGS = 0: (Accessing data EEPROM) FREE is ignored. The next WR command will initiate both a erase cycle and a write cycle.
bit 3
WRERR: EEPROM Error Flag bit 1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically on any set attempt (write `1') of the WR bit). 0 = The program or erase operation completed normally. WREN: Program/Erase Enable bit 1 = Allows program/erase cycles 0 = Inhibits programming/erasing of program Flash and data EEPROM WR: Write Control bit 1 = Initiates a program Flash or data EEPROM program/erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. The WR bit can only be set (not cleared) in software. 0 = Program/erase operation to the Flash or data EEPROM is complete and inactive. RD: Read Control bit 1 = Initiates an program Flash or data EEPROM read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate a program Flash or data EEPROM data read.
bit 2
bit 1
bit 0
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REGISTER 11-6:
W-0/0 bit 7 Legend: R = Readable bit S = Bit can only be set `1' = Bit is set bit 7-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared Data EEPROM Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the EECON1 register. The value written to this register is used to unlock the writes. There are specific timing requirements on these writes. Refer to Section 11.2.2 "Writing to the Data EEPROM Memory" for more information. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
EECON2: EEPROM CONTROL 2 REGISTER
W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 bit 0 EEPROM Control Register 2
TABLE 11-3:
Name EECON1 EEADRL EEADRH EEDATL EEDATH INTCON PIE2 PIR2
SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM
Bit 6 CFGS Bit 5 LWLO Bit 4 FREE Bit 3 WRERR Bit 2 WREN Bit 1 WR Bit 0 RD Register on Page
119 107* 118 118 118 118 91 93 97
Bit 7 EEPGD
EECON2 EEPROM Control Register 2 (not a physical register) EEADRL7 EEADRL6 EEADRL5 EEADRL4 EEADRL3 EEADRL2 EEADRL1 EEADRL0 -- -- GIE OSFIE OSFIF EEADRH6 EEADRH5 EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0 -- PEIE C2IE C2IF EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 TMR0IE C1IE C1IF INTE EEIE EEIF IOCIE BCL1IE BCL1IF TMR0IF -- -- INTF -- -- IOCIF CCP2IE CCP2IF EEDATL7 EEDATL6 EEDATL5 EEDATL4 EEDATL3 EEDATL2 EEDALT1 EEDATL0
Legend: -- = unimplemented read as `0'. Shaded cells are not used by Data EEPROM module. * Page provides register information.
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12.0 I/O PORTS
12.1 Alternate Pin Function
Depending on the device selected and peripherals enabled, there are two ports available. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation. These registers are: * TRISx registers (data direction register) * PORTx registers (reads the levels on the pins of the device) * LATx registers (output latch) The Data Latch (LATx registers) is useful for read-modify-write operations on the value that the I/O pins are driving. A write operation to the LATx register has the same affect as a write to the corresponding PORTx register. A read of the LATx register reads of the values held in the I/O PORT latches, while a read of the PORTx register reads the actual I/O pin value. Ports with analog functions also have an ANSELx register which can disable the digital input and save power. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 12-1. The Alternate Pin Function Control (APFCON0 and APFCON1) registers are used to steer specific peripheral input and output functions between different pins. The APFCON0 and APFCON1 registers are shown in Register 12-1 and Register 12-2. For this device family, the following functions can be moved between different pins. * * * * * * * * * RX/DT SDO1 SS1 (Slave Select 1) P2B CCP2/P2A P1D P1C CCP1/P1A TX/CK
These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected.
FIGURE 12-1:
GENERIC I/O PORT OPERATION
Read LATx D Write LATx Write PORTx Q
TRISx
CK Data Register
VDD
Data Bus I/O pin Read PORTx To peripherals ANSELx
VSS
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REGISTER 12-1:
R/W-0/0 RXDTSEL bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared RXDTSEL: Pin Selection bit 0 = RX/DT function is on RB1 1 = RX/DT function is on RB2 SDO1SEL: Pin Selection bit 0 = SDO1 function is on RB2 1 = SDO1 function is on RA6 SS1SEL: Pin Selection bit 0 = SS1 function is on RB5 1 = SS1 function is on RA5 P2BSEL: Pin Selection bit 0 = P2B function is on RB7 1 = P2B function is on RA6 CCP2SEL: Pin Selection bit 0 = CCP2/P2A function is on RB6 1 = CCP2/P2A function is on RA7 P1DSEL: Pin Selection bit 0 = P1D function is on RB7 1 = P1D function is on RA6 P1CSEL: Pin Selection bit 0 = P1C function is on RB6 1 = P1C function is on RA7 CCP1SEL: Pin Selection bit 0 = CCP1/P1A function is on RB3 1 = CCP1/P1A function is on RB0 PIC16F/LF1827 only. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
APFCON0: ALTERNATE PIN FUNCTION CONTROL REGISTER 0
R/W-0/0 SS1SEL R/W-0/0 P2BSEL(1) R/W-0/0 CCP2SEL(1) R/W-0/0 P1DSEL R/W-0/0 P1CSEL R/W-0/0 CCP1SEL bit 0
R/W-0/0 SDO1SEL
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
REGISTER 12-2:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-1 bit 0
APFCON1: ALTERNATE PIN FUNCTION CONTROL REGISTER 1
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0/0 TXCKSEL bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
Unimplemented: Read as `0' TXCKSEL: Pin Selection bit 0 = TX/CK function is on RB2 1 = TX/CK function is on RB5
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12.2 PORTA Registers
12.2.2 ANSELA REGISTER
PORTA is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 12-4). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). The exception is RA5, which is input only and its TRIS bit will always read as `1'. Example 12-1 shows how to initialize PORTA. Reading the PORTA register (Register 12-3) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATA). The TRISA register (Register 12-4) controls the PORTA pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. Note: The ANSELA register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'. The ANSELA register (Register 12-7) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELA bits has no affect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. The TRISA register (Register 12-4) controls the PORTA pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. Note: The ANSELA register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
EXAMPLE 12-1:
BANKSEL CLRF BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF PORTA PORTA LATA LATA ANSELA ANSELA TRISA 0Ch TRISA
INITIALIZING PORTA
; ;Init PORTA ;Data Latch ; ; ;digital I/O ; ;Set RA<3:2> as inputs ;and set RA<7:4,1:0> ;as outputs
12.2.1
WEAK PULL-UPS
Each of the PORTA pins has an individually configurable internal weak pull-up. Control bit WPUA<5> enables or disables the pull-up (see Register 12-6). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-up is disabled on a Power-on Reset by the WPUEN bit of the OPTION register.
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REGISTER 12-3:
R/W-x/x RA7 bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared RA<7:0>: PORTA I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
PORTA: PORTA REGISTER
R/W-x/x RA6 R-x/x RA5 R/W-x/x RA4 R/W-x/x RA3 R/W-x/x RA2 R/W-x/x RA1 R/W-x/x RA0 bit 0
Note 1:
REGISTER 12-4:
R/W-1/1 TRISA7 bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6
TRISA: PORTA TRI-STATE REGISTER
R/W-1/1 TRISA6 R-1/1 TRISA5 R/W-1/1 TRISA4 R/W-1/1 TRISA3 R/W-1/1 TRISA2 R/W-1/1 TRISA1 R/W-1/1 TRISA0 bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
TRISA<7:6>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output TRISA5: RA5 Port Tri-State Control bit This bit is always `1' as RA5 is an input only TRISA<4:0>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output
bit 5 bit 4-0
REGISTER 12-5:
R/W-x/u LATA7 bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6 bit 5 bit 4-0 Note 1:
LATA: PORTA DATA LATCH REGISTER
R/W-x/u LATA6 U-0 -- R/W-x/u LATA4 R/W-x/u LATA3 R/W-x/u LATA2 R/W-x/u LATA1 R/W-x/u LATA0 bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared LATA<7:6>: RA<7:6> Output Latch Value bits(1) Unimplemented: Read as `0 LATA<4:0>: RA<4:0> Output Latch Value bits(1)
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values.
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REGISTER 12-6:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6 bit 5 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0' WPUA5: Weak Pull-up RA5 Control bit If MCLRE in Configuration Word 1 = 0, MCLR is disabled): 1 = Weak Pull-up enabled(1) 0 = Weak Pull-up disabled If MCLRE in Configuration Word 1 = 1, MCLR is enabled): Weak Pull-up is always enabled. Unimplemented: Read as `0' Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in configured as an output. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
WPUA: WEAK PULL-UP PORTA REGISTER
U-0 -- R/W-1/1 WPUA5 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
bit 4-0 Note 1: 2:
REGISTER 12-7:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-5 bit 4-0
ANSELA: PORTA ANALOG SELECT REGISTER
U-0 -- U-0 -- R/W-1/1 ANSA4 R/W-1/1 ANSA3 R/W-1/1 ANSA2 R/W-1/1 ANSA1 R/W-1/1 ANSA0 bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
Unimplemented: Read as `0' ANSA<4:0>: Analog Select between Analog or Digital Function on pins RA<4:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin.
Note 1:
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12.2.3 PORTA FUNCTIONS AND OUTPUT PRIORITIES
RA5 Input only pin. RA6 1. 2. 3. 4. 5. 6. 7. RA7 1. 2. 3. 4. 5. OSC1/CLKIN (enabled by Configuration Word) P1C CCP2 (PIC16F/LF1827 only) P2A (PIC16F/LF1827 only) RA7 OSC2 (enabled by Configuration Word) CLKOUT CLKR SDO1 P1D P2B (PIC16F/LF1827 only) RA6 Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists. Analog input functions, such as ADC, comparator and CapSense inputs, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode with the priority shown below. RA0 1. 2. RA1 1. 2. RA2 1. 2. RA3 1. 2. 3. 4. RA4 1. 2. 3. 4. 5. SRNQ (SR latch) CCP4 (PIC16F/LF1827 only) T0CKI C2OUT (Comparator) RA4 SRQ (SR latch) CCP3 (PIC16F/LF1827 only) C1OUT (Comparator) RA3 DACOUT (DAC) RA2 SS2 (PIC16F/LF1827 only) RA1 SDO2 (PIC16F/LF1827 only) RA0
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TABLE 12-1:
Name ANSELA LATA OPTION_REG PORTA TRISA WPUA Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 -- LATA7 WPUEN RA7 TRISA7 -- Bit 6 -- LATA6 INTEDG RA6 TRISA6 -- Bit 5 -- -- TMR0CS RA5 TRISA5 WPUA5 Bit 4 ANSA4 LATA4 TMR0SE RA4 TRISA4 -- Bit 3 ANSA3 LATA3 PSA RA3 TRISA3 -- Bit 2 ANSA2 LATA2 PS2 RA2 TRISA2 -- Bit 1 ANSA1 LATA1 PS1 RA1 TRISA1 -- Bit 0 ANSA0 LATA0 PS0 RA0 TRISA0 -- Register on Page 125 124 177 124 124 125
-- = unimplemented locations read as `0'. Shaded cells are not used by PORTA.
TABLE 12-2:
Name Bits 13:8 7:0
SUMMARY OF CONFIGURATION WORD ASSOCIATED WITH PORTA
Bit -/7 -- CP Bit -/6 -- MCLRE Bit 13/5 FCMEN PWRTE Bit 12/4 IESO WDTE1 Bit 11/3 CLKOUTEN WDTE0 Bit 10/2 BOREN1 FOSC2 Bit 9/1 BOREN0 FOSC1 Bit 8/0 CPD FOSC0 Register on Page 50
CONFIG1 Legend:
-- = unimplemented locations read as `0'. Shaded cells are not used by PORTA.
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12.3 PORTB and TRISB Registers
12.3.3 ANSELB REGISTER
PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 12-9). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 12-2 shows how to initialize PORTB. Reading the PORTB register (Register 12-8) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. The TRISB register (Register 12-9) controls the PORTB pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISB register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. Example 12-2 shows how to initialize PORTB. The ANSELB register (Register 12-12) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELB bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELB bits has no affect on digital output functions. A pin with TRIS clear and ANSELB set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. The TRISB register (Register 12-9) controls the PORTB pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISB register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. Note: The ANSELB register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
EXAMPLE 12-2:
BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF
INITIALIZING PORTB
; ;Init PORTB ;Make RB<7:0> digital ; ;Set RB<7:4> as inputs ;and RB<3:0> as outputs ;
PORTB PORTB ANSELB ANSELB TRISB B'11110000' TRISB
12.3.1
INTERRUPT-ON-CHANGE
All of the PORTB pins are individually configurable as an interrupt-on-change pin. Control bits IOCB<7:0> enable or disable the interrupt function for each pin. The interrupt-on-change feature is disabled on a Power-on Reset. Reference Section 13.0 "Interrupt-On-Change" for more information.
12.3.2
WEAK PULL-UPS
Each of the PORTB pins has an individually configurable internal weak pull-up. Control bits WPUB<7:0> enable or disable each pull-up (see Register 12-11). Each weak pull-up is automatically turned off when the port pin is configured as an output. All pull-ups are disabled on a Power-on Reset by the WPUEN bit of the OPTION register.
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REGISTER 12-8:
R/W-x/x RB7 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared RB<7:0>: PORTB I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
PORTB: PORTB REGISTER
R/W-x/x RB5 R/W-x/x RB4 R/W-x/x RB3 R/W-x/x RB2 R/W-x/x RB1 R/W-x/x RB0 bit 0 RB6
R/W-x/x
REGISTER 12-9:
R/W-1/1 TRISB7 bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-0
TRISB: PORTB TRI-STATE REGISTER
R/W-1/1 TRISB5 R/W-1/1 TRISB4 R/W-1/1 TRISB3 R/W-1/1 TRISB2 R/W-1/1 TRISB1 R/W-1/1 TRISB0 bit 0
R/W-1/1 TRISB6
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
TRISB<7:0>: PORTB Tri-State Control bit 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output
REGISTER 12-10: LATB: PORTB DATA LATCH REGISTER
R/W-x/u LATB7 bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-0 Note 1: W = Writable bit x = Bit is unknown `0' = Bit is cleared LATB<7:0>: PORTB Output Latch Value bits(1) Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets R/W-x/u LATB6 R/W-x/u LATB5 R/W-x/u LATB4 R/W-x/u LATB3 R/W-x/u LATB2 R/W-x/u LATB1 R/W-x/u LATB0 bit 0
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REGISTER 12-11: WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1/1 WPUB7 bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared WPUB<7:0>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in configured as an output. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets R/W-1/1 WPUB6 R/W-1/1 WPUB5 R/W-1/1 WPUB4 R/W-1/1 WPUB3 R/W-1/1 WPUB2 R/W-1/1 WPUB1 R/W-1/1 WPUB0 bit 0
Note 1: 2:
REGISTER 12-12: ANSELB: PORTB ANALOG SELECT REGISTER
R/W-1/1 ANSB7 bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-1 W = Writable bit x = Bit is unknown `0' = Bit is cleared ANSB<7:1>: Analog Select between Analog or Digital Function on Pins RB<7:1>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Unimplemented: Read as `0' When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets R/W-1/1 ANSB6 R/W-1/1 ANSB5 R/W-1/1 ANSB4 R/W-1/1 ANSB3 R/W-1/1 ANSB2 R/W-1/1 ANSB1
U-0 --
bit 0
bit 0 Note 1:
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12.3.4 PORTB FUNCTIONS AND OUTPUT PRIORITIES
RB3 1. 2. 3. RB4 1. 2. 3. RB5 1. 2. 3. 4. 5. RB6 P1A RB0 SDA1 RX/DT RB1 SDA2 (PIC16F/LF1827 only) TX/CK RX/DT SDO1 RB2 1. 2. 3. 4. 5. 6. RB7 1. 2. 3. 4. 5. ICSPDAT (Programming) T1OSO P1D P2B (PIC16F/LF1827 only) RB7 ICSPCLK (Programming) T1OSI P1C CCP2 (PIC16F/LF1827 only) P2A (PIC16F/LF1827 only) RB6 SCL2 (PIC16F/LF1827 only) TX/CK SCK2 (PIC16F/LF1827 only) P1B RB5 SCL1 SCK1 RB4 MDOUT CCP1/P1A RB3 Each PORTB pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists. Analog input and some digital input functions are not included in the list below. These input functions can remain active when the pin is configured as an output. Certain digital input functions, such as the EUSART RX signal, override other port functions and are included in the priority list. RB0 1. 2. RB1 1. 2. 3. RB2 1. 2. 3. 4. 5.
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TABLE 12-3:
Name ANSELB LATB OPTION_REG PORTB TRISB WPUB Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7 ANSB7 LATB7 WPUEN RB7 TRISB7 WPUB7 Bit 6 ANSB6 LATB6 INTEDG RB6 TRISB6 WPUB6 Bit 5 ANSB5 LATB5 TMR0CS RB5 TRISB5 WPUB5 Bit 4 ANSB4 LATB4 TMR0SE RB4 TRISB4 WPUB4 Bit 3 ANSB3 LATB3 PSA RB3 TRISB3 WPUB3 Bit 2 ANSB2 LATB2 PS2 RB2 TRISB2 WPUB2 Bit 1 ANSB1 LATB1 PS1 RB1 TRISB1 WPUB1 Bit 0 -- LATB0 PS0 RB0 TRISB0 WPUB0 Register on Page 130 129 177 129 129 130
-- = unimplemented locations read as `0'. Shaded cells are not used by PORTB.
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13.0 INTERRUPT-ON-CHANGE
13.3 Interrupt Flags
The PORTB pins can be configured to operate as Interrupt-on-change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual PORTB pin can be configured to generate an interrupt. The interrupt-on-change module has the following features: * * * * Interrupt-on-change enable (Master Switch) Individual pin configuration Rising and falling edge detection Individual pin interrupt flags The IOCBFx bits located in the IOCBF register are status flags that correspond to the Interrupt-on-change pins of the port. If an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set. The IOCIF bit of the INTCON register reflects the status of all IOCBFx bits.
13.4
Clearing Interrupt Flags
Figure 13-1 is a block diagram of the IOC module.
13.1
Enabling the Module
The individual status flags, (IOCBFx bits), can be cleared by resetting them to zero. If another edge is detected during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the value actually being written. In order to ensure that no detected edge is lost while clearing flags, only AND operations masking out known changed bits should be performed. The following sequence is an example of what should be performed.
To allow individual port pins to generate an interrupt, the IOCIE bit of the INTCON register must be set. If the IOCIE bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated.
13.2
Individual Pin Configuration
EXAMPLE 13-1:
MOVLW XORWF ANDWF 0xff IOCBF, W IOCBF, F
For each port pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a rising edge, the associated IOCBPx bit of the IOCBP register is set. To enable a pin to detect a falling edge, the associated IOCBNx bit of the IOCBN register is set. A pin can be configured to detect rising and falling edges simultaneously by setting both the IOCBPx bit and the IOCBNx bit of the IOCBP and IOCBN registers, respectively.
13.5
Operation in Sleep
The interrupt-on-change interrupt sequence will wake the device from Sleep mode, if the IOCIE bit is set. If an edge is detected while in Sleep mode, the IOCBF register will be updated prior to the first instruction executed out of Sleep.
FIGURE 13-1:
INTERRUPT-ON-CHANGE BLOCK DIAGRAM
IOCIE
IOCBNx
D CK R
Q
IOCBFx From all other IOCBFx individual pin detectors IOC Interrupt to CPU Core
RBx
IOCBPx
D CK R
Q
Q2 Clock Cycle
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REGISTER 13-1:
R/W-0/0 IOCBP7 bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared IOCBP<7:0>: Interrupt-on-Change Positive Edge Enable bits 1 = Interrupt-on-change enabled on the pin for a positive going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 = Interrupt-on-change disabled for the associated pin. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
IOCBP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER
R/W-0/0 IOCBP5 R/W-0/0 IOCBP4 R/W-0/0 IOCBP3 R/W-0/0 IOCBP2 R/W-0/0 IOCBP1 R/W-0/0 IOCBP0 bit 0
R/W-0/0 IOCBP6
REGISTER 13-2:
R/W-0/0 IOCBN7 bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-0
IOCBN: INTERRUPT-ON-CHANGE NEGATIVE EDGE REGISTER
R/W-0/0 IOCBN5 R/W-0/0 IOCBN4 R/W-0/0 IOCBN3 R/W-0/0 IOCBN2 R/W-0/0 IOCBN1 R/W-0/0 IOCBN0 bit 0
R/W-0/0 IOCBN6
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
IOCBN<7:0>: Interrupt-on-Change Negative Edge Enable bits 1 = Interrupt-on-change enabled on the pin for a negative going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 = Interrupt-on-change disabled for the associated pin.
REGISTER 13-3:
R/W/HS-0/0 IOCBF7 bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-0
IOCBF: INTERRUPT-ON-CHANGE FLAG REGISTER
R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCBF5 IOCBF4 IOCBF3 R/W/HS-0/0 IOCBF2 R/W/HS-0/0 IOCBF1 R/W/HS-0/0 IOCBF0 bit 0
R/W/HS-0/0 IOCBF6
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets HS - Bit is set in hardware
IOCBF<7:0>: Interrupt-on-Change Flag bits 1 = An enabled change was detected on the associated pin. Set when IOCBPx = 1 and a rising edge was detected on RBx, or when IOCBNx = 1 and a falling edge was detected on RBx. 0 = No change was detected, or the user cleared the detected change.
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TABLE 13-1:
Name ANSELB INTCON IOCBF IOCBN IOCBP TRISB
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE
Bit 7 ANSB7 GIE IOCBF7 IOCBN7 IOCBP7 TRISB7 Bit 6 ANSB6 PEIE IOCBF6 IOCBN6 IOCBP6 TRISB6 Bit 5 ANSB5 TMR0IE IOCBF5 IOCBN5 IOCBP5 TRISB5 Bit 4 ANSB4 INTE IOCBF4 IOCBN4 IOCBP4 TRISB4 Bit 3 ANSB3 IOCIE IOCBF3 IOCBN3 IOCBP3 TRISB3 Bit 2 ANSB2 TMR0IF IOCBF2 IOCBN2 IOCBP2 TRISB2 Bit 1 ANSB1 INTF IOCBF1 IOCBN1 IOCBP1 TRISB1 Bit 0 -- IOCIF IOCBF0 IOCBN0 IOCBP0 TRISB0 Register on Page 130 91 134 134 134 129
Legend: -- = unimplemented locations read as `0'. Shaded cells are not used by interrupt-on-change.
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14.0 FIXED VOLTAGE REFERENCE (FVR)
14.1 Independent Gain Amplifiers
The output of the FVR supplied to the ADC, Comparators, and DAC is routed through two independent programmable gain amplifiers. Each amplifier can be configured to amplify the reference voltage by 1x, 2x or 4x, to produce the three possible voltage levels. The ADFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the ADC module. Reference Section 15.0 "Analog-to-Digital Converter (ADC) Module"for additional information. The CDAFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the DAC and Comparator module. Reference Section 16.0 "Digital-to-Analog Converter (DAC) Module" and Section 18.0 "Comparator Module" for additional information.
The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels. The output of the FVR can be configured to supply a reference voltage to the following: * * * * ADC input channel ADC positive reference Comparator positive input Digital-to-Analog Converter (DAC)
The FVR can be enabled by setting the FVREN bit of the FVRCON register.
14.2
FVR Stabilization Period
When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the circuits stabilize and are ready for use, the FVRRDY bit of the FVRCON register will be set. See Section 29.0 "Electrical Specifications" for the minimum delay requirement.
FIGURE 14-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
ADFVR<1:0> 2
X1 X2 X4
FVR BUFFER1 (To ADC Module)
CDAFVR<1:0>
2
X1 X2 X4
FVR BUFFER2 (To Comparators, DAC)
FVREN FVRRDY
+ _
1.024V Fixed Reference
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REGISTER 14-1:
R/W-0/0 FVREN bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition
FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER
R-q/q R/W-0/0 Reserved R/W-0/0 Reserved R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 bit 0 CDAFVR<1:0> ADFVR<1:0>
FVRRDY(1)
FVREN: Fixed Voltage Reference Enable bit 0 = Fixed Voltage Reference is disabled 1 = Fixed Voltage Reference is enabled FVRRDY: Fixed Voltage Reference Ready Flag bit(1) 0 = Fixed Voltage Reference output is not ready or not enabled 1 = Fixed Voltage Reference output is ready for use Reserved: Read as `0'. Maintain these bits clear. CDAFVR<1:0>: Comparator and DAC Fixed Voltage Reference Selection bit 00 = Comparator and DAC Fixed Voltage Reference Peripheral output is off. 01 = Comparator and DAC Fixed Voltage Reference Peripheral output is 1x (1.024V) 10 = Comparator and DAC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 11 = Comparator and DAC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) ADFVR<1:0>: ADC Fixed Voltage Reference Selection bit 00 = ADC Fixed Voltage Reference Peripheral output is off. 01 = ADC Fixed Voltage Reference Peripheral output is 1x (1.024V) 10 = ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 11 = ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) FVRRDY is always `1' on devices with LDO (PIC16F1826/27). Fixed Voltage Reference output cannot exceed VDD.
bit 6
bit 5-4 bit 3-2
bit 1-0
Note 1: 2:
TABLE 14-1:
Name FVRCON Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH THE FVR MODULE
Bit 7 FVREN Bit 6 FVRRDY Bit 5 Reserved Bit 4 Reserved Bit 3 CDAFVR1 Bit 2 CDAFVR0 Bit 1 ADFVR1 Bit 0 ADFVR0 Register on page 138
Shaded cells are unused by the FVR module.
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15.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE
The ADC voltage reference is software selectable to be either internally generated or externally supplied. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep.
The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESH:ADRESL register pair). Figure 15-1 shows the block diagram of the ADC.
FIGURE 15-1:
ADC BLOCK DIAGRAM
VREF-
ADNREF = 1 ADNREF = 0
VDD
VSS ADPREF = 00 ADPREF = 11 VREF+ ADPREF = 10
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 DAC FVR Buffer1
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 11110 11111 ADON VSS ADRESH ADFM 0 = Left Justify 1 = Right Justify 16 ADRESL GO/DONE ADC 10
CHS<4:0>
Note:
When ADON = 0, all multiplexer inputs are disconnected.
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15.1 ADC Configuration
15.1.4 CONVERSION CLOCK
When configuring and using the ADC the following functions must be considered: * * * * * * Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There are seven possible clock options: * * * * * * * FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (dedicated internal oscillator)
15.1.1
PORT CONFIGURATION
The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 12.0 "I/O Ports" for more information. Note: Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current.
The time to complete one bit conversion is defined as TAD. One full 10-bit conversion requires 11.5 TAD periods as shown in Figure 15-2. For correct conversion, the appropriate TAD specification must be met. Refer to the A/D conversion requirements in Section 29.0 "Electrical Specifications" for more information. Table 15-1 gives examples of appropriate ADC clock selections. Note: Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result.
15.1.2
CHANNEL SELECTION
There are up to 14 channel selections available: * AN<11:0> pins * DAC Output * FVR (Fixed Voltage Reference) Output Refer to Section 16.0 "Digital-to-Analog Converter (DAC) Module" and Section 14.0 "Fixed Voltage Reference (FVR)" for more information on these channel selections. The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section 15.2 "ADC Operation" for more information.
15.1.3
ADC VOLTAGE REFERENCE
The ADPREF bits of the ADCON1 register provides control of the positive voltage reference. The positive voltage reference can be: * * * * VREF+ pin VDD FVR 2.028V FVR 4.096V (Not available on LF devices)
The ADNREF bits of the ADCON1 register provides control of the negative voltage reference. The negative voltage reference can be: * VREF- pin * VSS See Section 14.0 "Fixed Voltage Reference (FVR)" for more details on the fixed voltage reference.
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TABLE 15-1:
ADC Clock Source Fosc/2 Fosc/4 Fosc/8 Fosc/16 Fosc/32 Fosc/64 FRC Legend: Note 1: 2: 3: 4:
ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
Device Frequency (FOSC) 32 MHz 62.5ns(2) 125 ns
(2)
ADC Clock Period (TAD) ADCS<2:0> 000 100 001 101 010 110 x11 20 MHz 100 ns(2) 200 ns
(2)
16 MHz 125 ns(2) 250 ns
(2)
8 MHz 250 ns(2) 500 ns
(2)
4 MHz 500 ns(2) 1.0 s 2.0 s 4.0 s 8.0 s
(3) (3)
1 MHz 2.0 s 4.0 s 8.0 s(3) 16.0 s(3) 32.0 s(3) 64.0 s(3) 1.0-6.0 s(1,4)
0.5 s(2) 800 ns 1.0 s 2.0 s 1.0-6.0 s(1,4)
400 ns(2) 800 ns 1.6 s 3.2 s 1.0-6.0 s(1,4)
0.5 s(2) 1.0 s 2.0 s 4.0 s 1.0-6.0 s(1,4)
1.0 s 2.0 s 4.0 s 8.0 s
(3)
16.0 s
1.0-6.0 s(1,4)
1.0-6.0 s(1,4)
Shaded cells are outside of recommended range. The FRC source has a typical TAD time of 1.6 s for VDD. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the device in Sleep mode.
FIGURE 15-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b4 b1 b0 b6 b7 b2 b9 b8 b3 b5 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input.
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15.1.5 INTERRUPTS 15.1.6 RESULT FORMATTING
The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. Note 1: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. 2: The ADC operates during Sleep only when the FRC oscillator is selected. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the GIE and PEIE bits of the INTCON register must be disabled. If the GIE and PEIE bits of the INTCON register are enabled, execution will switch to the Interrupt Service Routine. Please refer to Section 15.1.5 "Interrupts" for more information. The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format. Figure 15-3 shows the two output formats.
FIGURE 15-3:
10-BIT A/D CONVERSION RESULT FORMAT
ADRESH ADRESL LSB bit 0 10-bit A/D Result bit 7 bit 0 Unimplemented: Read as `0' LSB bit 0 bit 7 10-bit A/D Result bit 0
(ADFM = 0)
MSB bit 7
(ADFM = 1) bit 7 Unimplemented: Read as `0'
MSB
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15.2
15.2.1
ADC Operation
STARTING A CONVERSION
15.2.4
ADC OPERATION DURING SLEEP
To enable the ADC module, the ADON bit of the ADCON0 register must be set to a `1'. Setting the GO/ DONE bit of the ADCON0 register to a `1' will start the Analog-to-Digital conversion. Note: The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 15.2.6 "A/D Conversion Procedure".
The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC clock source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set.
15.2.2
COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will: * Clear the GO/DONE bit * Set the ADIF Interrupt Flag bit * Update the ADRESH and ADRESL registers with new conversion result
15.2.5
SPECIAL EVENT TRIGGER
15.2.3
TERMINATING A CONVERSION
If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software. The ADRESH and ADRESL registers will be updated with the partially complete Analog-to-Digital conversion sample. Incomplete bits will match the last bit converted. Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated.
The Special Event Trigger of the CCPx/ECCPX module allows periodic ADC measurements without software intervention. When this trigger occurs, the GO/DONE bit is set by hardware and the Timer1 counter resets to zero.
TABLE 15-2:
Device
SPECIAL EVENT TRIGGER
CCPx/ECCPx ECCP1 CCP4
PIC16F/LF1826 PIC16F/LF1827
Using the Special Event Trigger does not assure proper ADC timing. It is the user's responsibility to ensure that the ADC timing requirements are met. Refer to Section 23.0 "Capture/Compare/PWM Modules" for more information.
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15.2.6 A/D CONVERSION PROCEDURE EXAMPLE 15-1: A/D CONVERSION
This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. Configure Port: * Disable pin output driver (Refer to the TRIS register) * Configure pin as analog (Refer to the ANSEL register) Configure the ADC module: * Select ADC conversion clock * Configure voltage reference * Select ADC input channel * Turn on ADC module Configure ADC interrupt (optional): * Clear ADC interrupt flag * Enable ADC interrupt * Enable peripheral interrupt * Enable global interrupt(1) Wait the required acquisition time(2). Start conversion by setting the GO/DONE bit. Wait for ADC conversion to complete by one of the following: * Polling the GO/DONE bit * Waiting for the ADC interrupt (interrupts enabled) Read ADC Result. Clear the ADC interrupt flag (required if interrupt is enabled). Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section 15.3 "A/D Acquisition Requirements".
;This code block configures the ADC ;for polling, Vdd and Vss references, Frc ;clock and AN0 input. ; ;Conversion start & polling for completion ; are included. ; BANKSEL ADCON1 ; MOVLW B'11110000' ;Right justify, Frc ;clock MOVWF ADCON1 ;Vdd and Vss Vref BANKSEL TRISA ; BSF TRISA,0 ;Set RA0 to input BANKSEL ANSEL ; BSF ANSEL,0 ;Set RA0 to analog BANKSEL ADCON0 ; MOVLW B'00000001' ;Select channel AN0 MOVWF ADCON0 ;Turn ADC On CALL SampleTime ;Acquisiton delay BSF ADCON0,ADGO ;Start conversion BTFSC ADCON0,ADGO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space
2.
3.
4. 5. 6.
7. 8.
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15.2.7 ADC REGISTER DEFINITIONS
The following registers are used to control the operation of the ADC.
REGISTER 15-1:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 bit 6-2
ADCON0: A/D CONTROL REGISTER 0
R/W-0/0 R/W-0/0 CHS<4:0> R/W-0/0 R/W-0/0 R/W-0/0 GO/DONE R/W-0/0 ADON bit 0
R/W-0/0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
Unimplemented: Read as `0' CHS<4:0>: Analog Channel Select bits 00000 = AN0 00001 = AN1 00010 = AN2 00011 = AN3 00100 = AN4 00101 = AN5 00110 = AN6 00111 = AN7 01000 = AN8 01001 = AN9 01010 = AN10 01011 = AN11 01100 = Reserved. No channel connected. * * * 11101 = Reserved. No channel connected. 11110 = DAC output(1) 11111 = FVR (Fixed Voltage Reference) Buffer 1 Output(2) GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current See Section 16.0 "Digital-to-Analog Converter (DAC) Module" for more information. See Section 14.0 "Fixed Voltage Reference (FVR)" for more information.
bit 1
bit 0
Note 1: 2:
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REGISTER 15-2:
R/W-0/0 ADFM bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared ADFM: A/D Result Format Select bit 1 = Right justified. Six Most Significant bits of ADRESH are set to `0' when the conversion result is loaded. 0 = Left justified. Six Least Significant bits of ADRESL are set to `0' when the conversion result is loaded. ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (clock supplied from a dedicated RC oscillator) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC (clock supplied from a dedicated RC oscillator) Unimplemented: Read as `0' ADNREF: A/D Negative Voltage Reference Configuration bit 0 = VREF- is connected to VSS 1 = VREF- is connected to external VREF- pin(1) ADPREF<1:0>: A/D Positive Voltage Reference Configuration bits 00 = VREF+ is connected to VDD 01 = Reserved 10 = VREF+ is connected to external VREF+ pin(1) 11 = VREF+ is connected to internal Fixed Voltage Reference (FVR) module When selecting the FVR or the VREF+ pin as the source of the positive reference, be aware that a minimum voltage specification exists. See Section 29.0 "Electrical Specifications" for details. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
ADCON1: A/D CONTROL REGISTER 1
R/W-0/0 ADCS<2:0> R/W-0/0 U-0 -- R/W-0/0 ADNREF R/W-0/0 R/W-0/0 bit 0 ADPREF<1:0>
R/W-0/0
bit 6-4
bit 3 bit 2
bit 1-0
Note 1:
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REGISTER 15-3:
R/W-x/u bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u bit 0 ADRES<9:2>
R/W-x/u
REGISTER 15-4:
R/W-x/u bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6 bit 5-0 ADRES<1:0>
ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0
R/W-x/u -- R/W-x/u -- R/W-x/u -- R/W-x/u -- R/W-x/u -- R/W-x/u -- bit 0
R/W-x/u
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result Reserved: Do not use.
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REGISTER 15-5:
R/W-x/u -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-2 bit 1-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared Reserved: Do not use. ADRES<9:8>: ADC Result Register bits Upper 2 bits of 10-bit conversion result U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1
R/W-x/u -- R/W-x/u -- R/W-x/u -- R/W-x/u -- R/W-x/u R/W-x/u bit 0 -- ADRES<9:8>
R/W-x/u
REGISTER 15-6:
R/W-x/u bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-0
ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u bit 0 ADRES<7:0>
R/W-x/u
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
ADRES<7:0>: ADC Result Register bits Lower 8 bits of 10-bit conversion result
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15.3 A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 15-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 15-4. The maximum recommended impedance for analog sources is 10 k. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 15-1 may be used. This equation assumes that 1/2 LSb error is used (1,024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution.
EQUATION 15-1: Assumptions:
ACQUISITION TIME EXAMPLE Temperature = 50C and external impedance of 10k 5.0V VDD
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF = 2s + TC + Temperature - 25C 0.05s/C The value for TC can be approximated with the following equations:
1 VAPPLIED 1 - -------------------------- = VCHOLD n+1 2 -1
--------- RC VAPPLIED 1 - e = VCHOLD - Tc - TC
;[1] VCHOLD charged to within 1/2 lsb
;[2] VCHOLD charge response to VAPPLIED
-------- 1 RC VAPPLIED 1 - e = VAPPLIED 1 - -------------------------- ;combining [1] and [2] n+1 2 -1
Note: Where n = number of bits of the ADC. Solving for TC:
TC = - CHOLD RIC + RSS + RS ln(1/511) = - 10pF 1k + 7k + 10k ln(0.001957)
= 1.12 s Therefore: TACQ = 2s + 1.12s + 50C- 25C 0.05s/C = 4.42s
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification.
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FIGURE 15-4: ANALOG INPUT MODEL
Analog Input pin CPIN 5 pF VDD VT 0.6V RIC 1k I LEAKAGE(1) Sampling Switch SS Rss CHOLD = 10 pF VSS/VREF-
Rs VA
VT 0.6V
Legend: CHOLD CPIN
= Sample/Hold Capacitance = Input Capacitance
6V 5V VDD 4V 3V 2V
RSS
I LEAKAGE = Leakage current at the pin due to various junctions = Interconnect Resistance RIC RSS = Resistance of Sampling Switch SS VT = Sampling Switch = Threshold Voltage
5 6 7 8 9 10 11 Sampling Switch (k)
Note 1: Refer to Section 33.0 "Electrical Specifications".
FIGURE 15-5:
ADC TRANSFER FUNCTION
Full-Scale Range 3FFh 3FEh 3FDh ADC Output Code 3FCh 3FBh
03h 02h 01h 00h 0.5 LSB VREFZero-Scale Transition Full-Scale Transition Analog Input Voltage 1.5 LSB
VREF+
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TABLE 15-3:
Name ADCON0 ADCON1 ADRESH ADRESL ANSELA ANSELB CCPxCON INTCON PIE1 PIR1 TRISA TRISB FVRCON DACCON0 DACCON1 Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH ADC
Bit 7 -- ADFM Bit 6 CHS4 ADCS2 Bit 5 CHS3 ADCS1 Bit 4 CHS2 ADCS0 Bit 3 CHS1 -- Bit 2 CHS0 ADNREF Bit 1 GO/DONE ADPREF1 Bit 0 ADON ADPREF0 Register on Page 145 145 147, 148 147, 148 -- ANSB5 DCxB1 TMR0IE RCIE RCIF TRISA5 TRISB5 Reserved DACOE -- ANSA4 ANSB4 DCxB0 INTE TXIE TXIF TRISA4 TRISB4 Reserved -- DACR4 ANSA3 ANSB3 CCPxM3 IOCE SSP1IE SSP1IF TRISA3 TRISB3 CDAFVR1 DACPSS1 DACR3 ANSA2 ANSB2 CCPxM2 TMR0IF CCP1IE CCP1IF TRISA2 TRISB2 CDAFVR0 DACPSS0 DACR2 ANSA1 ANSB1 CCPxM1 INTF TMR2IE TMR2IF TRISA1 TRISB1 ADFVR1 -- DACR1 ANSA0 -- CCPxM0 IOCF TMR1IE TMR1IF TRISA0 TRISB0 ADFVR0 DACNSS DACR0 125 130 228 91 92 96 124 129 137 157 157
A/D Result Register High A/D Result Register Low -- ANSB7 PxM1 GIE TMR1GIE TMR1GIF TRISA7 TRISB7 FVREN DACEN -- -- ANSB6 PxM0 PEIE ADIE ADIF TRISA6 TRISB6 FVRRDY DACLPS --
-- = unimplemented read as `0'. Shaded cells are not used for ADC module.
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16.0 DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE
16.3.1 OUTPUT CLAMPED TO POSITIVE VOLTAGE SOURCE
The DAC output voltage can be set to VSRC+ with the least amount of power consumption by performing the following: * Clearing the DACEN bit in the DACCON0 register. * Setting the DACLPS bit in the DACCON0 register. * Configuring the DACPSS bits to the proper positive source. * Configuring the DACR<4:0> bits to `11111' in the DACCON1 register. This is also the method used to output the voltage level from the FVR to an output pin. See Section 16.4 "DAC Voltage Reference Output" for more information. Reference Figure 16-1 for output clamping examples.
The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels. The input of the DAC can be connected to: * External VREF pins * VDD supply voltage * FVR (Fixed Voltage Reference) The output of the DAC can be configured to supply a reference voltage to the following: * Comparator positive input * ADC input channel * DACOUT pin The Digital-to-Analog Converter (DAC) can be enabled by setting the DACEN bit of the DACCON0 register.
16.3.2
OUTPUT CLAMPED TO NEGATIVE VOLTAGE SOURCE
16.1
Output Voltage Selection
The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 register. The DAC output voltage is determined by the following equations:
The DAC output voltage can be set to VSRC- with the least amount of power consumption by performing the following: * Clearing the DACEN bit in the DACCON0 register. * Clearing the DACLPS bit in the DACCON0 register. * Configuring the DACNSS bits to the proper negative source. * Configuring the DACR<4:0> bits to `00000' in the DACCON1 register. This allows the comparator to detect a zero-crossing while not consuming additional current through the DAC module. Reference Figure 16-1 for output clamping examples.
EQUATION 16-1:
DAC OUTPUT VOLTAGE
2
DACR<4:0> VOUT = VSOURCE+ - VSOURCE- ------------------------------ + VSRC- 5 Note: VSOURCE+ can equal FVR Buffer 2, VDD or VREF+. VSOURCE- can equal VSS or VREF-.
16.2
Ratiometric Output Level
The DAC output value is derived using a resistor ladder with each end of the ladder tied to a positive and negative voltage reference input source. If the voltage of either input source fluctuates, a similar fluctuation will result in the DAC output value. The value of the individual resistors within the ladder can be found in Section 29.0 "Electrical Specifications".
16.3
Low Power Voltage State
In order for the DAC module to consume the least amount of power, one of the two voltage reference input sources to the resistor ladder must be disconnected. Either the positive voltage source, (VSRC+), or the negative voltage source, (VSRC-) can be disabled. The negative voltage source is disabled by setting the DACLPS bit in the DACCON0 register. Clearing the DACLPS bit in the DACCON0 register disables the positive voltage source.
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FIGURE 16-1: OUTPUT VOLTAGE CLAMPING EXAMPLES
Output Clamped to Negative Voltage Source VSRC+ R R DACEN = 0 DACLPS = 1 DAC Voltage Ladder (see Figure 16-2) R VSRCVSRCDACEN = 0 DACLPS = 0 DACR<4:0> = 11111 R R DAC Voltage Ladder (see Figure 16-2) R DACR<4:0> = 00000 Output Clamped to Positive Voltage Source VSRC+
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16.4 DAC Voltage Reference Output
The DAC can be output to the DACOUT pin by setting the DACOE bit of the DACCON0 register to `1'. Selecting the DAC reference voltage for output on the DACOUT pin automatically overrides the digital output buffer and digital input threshold detector functions of that pin. Reading the DACOUT pin when it has been configured for DAC reference voltage output will always return a `0'. Due to the limited current drive capability, a buffer must be used on the DAC voltage reference output for external connections to DACOUT. Figure 16-3 shows an example buffering technique.
FIGURE 16-2:
DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM
Digital-to-Analog Converter (DAC) FVR BUFFER2 VDD VREF+
VSRC+
5 R R 2 R R 32 Steps R R R 32-to-1 MUX R
DACR<4:0>
DACPSS<1:0> DACEN DACLPS
DAC (To Comparator and ADC Modules)
DACOUT DACOE
DACNSS
VREFVSS
VSRC-
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FIGURE 16-3: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC(R) MCU
DAC Module
R Voltage Reference Output Impedance DACOUT
+ -
Buffered DAC Output
16.5
Operation During Sleep
When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the DACCON0 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled.
16.6
Effects of a Reset
A device Reset affects the following: * DAC is disabled. * DAC output voltage is removed from the DACOUT pin. * The DACR<4:0> range select bits are cleared.
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REGISTER 16-1:
R/W-0/0 DACEN bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared DACEN: DAC Enable bit 1 = DAC is enabled 0 = DAC is disabled DACLPS: DAC Low-Power Voltage State Select bit 1 = DAC Positive reference source selected 0 = DAC Negative reference source selected DACOE: DAC Voltage Output Enable bit 1 = DAC voltage level is also an output on the DACOUT pin 0 = DAC voltage level is disconnected from the DACOUT pin Unimplemented: Read as `0' DACPSS<1:0>: DAC Positive Source Select bits 00 = VDD 01 = VREF+ 10 = FVR Buffer2 output 11 = Reserved, do not use Unimplemented: Read as `0' DACNSS: DAC Negative Source Select bits 1 = VREF0 = VSS U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0
R/W-0/0 DACOE U-0 -- R/W-0/0 R/W-0/0 U-0 -- R/W-0/0 DACNSS bit 0 DACPSS<1:0>
R/W-0/0 DACLPS
bit 6
bit 5
bit 4 bit 3-2
bit 1 bit 0
REGISTER 16-2:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-5 bit 4-0 Note 1:
DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1
U-0 -- U-0 -- R/W-0/0 R/W-0/0 R/W-0/0 DACR<4:0> bit 0 R/W-0/0 R/W-0/0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
Unimplemented: Read as `0' DACR<4:0>: DAC Voltage Output Select bits VOUT = ((VSRC+) - (VSRC-))*(DACR<4:0>/(25)) + VSRCThe output select bits are always right justified to ensure that any number of bits can be used without affecting the register layout.
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TABLE 16-1:
Name FVRCON DACCON0 DACCON1 Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE
Bit 7 FVREN DACEN -- Bit 6 FVRRDY DACLPS -- Bit 5 Reserved DACOE -- Bit 4 Reserved -- DACR4 Bit 3 CDAFVR1 DACPSS1 DACR3 Bit 2 CDAFVR0 DACPSS0 DACR2 Bit 1 ADFVR1 -- DACR1 Bit 0 ADFVR0 DACNSS DACR0 Register on page 138 157 157
-- = unimplemented, read as `0'. Shaded cells are unused with the DAC module.
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17.0 SR LATCH
17.2 Latch Output
The module consists of a single SR latch with multiple Set and Reset inputs as well as separate latch outputs. The SR latch module includes the following features: * * * * Programmable input selection SR latch output is available externally Separate Q and Q outputs Firmware Set and Reset The SRQEN and SRNQEN bits of the SRCON0 register control the Q and Q latch outputs. Both of the SR latch outputs may be directly output to an I/O pin at the same time. The applicable TRIS bit of the corresponding port must be cleared to enable the port pin output driver.
The SR latch can be used in a variety of analog applications, including oscillator circuits, one-shot circuit, hysteretic controllers, and analog timing applications.
17.3
Effects of a Reset
17.1
Latch Operation
Upon any device Reset, the SR latch output is not initialized to a known state. The user's firmware is responsible for initializing the latch output before enabling the output pins.
The latch is a Set-Reset latch that does not depend on a clock source. Each of the Set and Reset inputs are active-high. The latch can be Set or Reset by: * * * * * Software control (SRPS and SRPR bits) Comparator C1 output (SYNCC1OUT) Comparator C2 output (SYNCC2OUT) SRI pin Programmable clock (SRCLK)
The SRPS and the SRPR bits of the SRCON0 register may be used to Set or Reset the SR latch, respectively. The latch is Reset-dominant. Therefore, if both Set and Reset inputs are high, the latch will go to the Reset state. Both the SRPS and SRPR bits are self resetting which means that a single write to either of the bits is all that is necessary to complete a latch Set or Reset operation. The output from Comparator C1 or C2 can be used as the Set or Reset inputs of the SR latch. The output of either Comparator can be synchronized to the Timer1 clock source. See Section 18.0 "Comparator Module" and Section 20.0 "Timer1 Module with Gate Control" for more information. An external source on the SRI pin can be used as the Set or Reset inputs of the SR latch. An internal clock source is available that can periodically Set or Reset the SR latch. The SRCLK<2:0> bits in the SRCON0 register are used to select the clock source period. The SRSCKE and SRRCKE bits of the SRCON1 register enable the clock source to Set or Reset the SR latch, respectively. Note: Enabling both the Set and Reset inputs from any one source at the same time may result in indeterminate operation, as the Reset dominance cannot be assured.
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FIGURE 17-1:
SRPS
SR LATCH SIMPLIFIED BLOCK DIAGRAM
Pulse Gen(2) SRLEN SRQEN
SRI SRSPE SRCLK SRSCKE SYNCC2OUT(3) SRSC2E SYNCC1OUT(3) SRSC1E SRPR Pulse Gen(2) SR Latch(1) S Q SRQ
SRI SRRPE SRCLK SRRCKE SYNCC2OUT(3) SRRC2E SYNCC1OUT(3) SRRC1E R Q SRNQ SRLEN SRNQEN
Note 1: 2: 3:
If R = 1 and S = 1 simultaneously, Q = 0, Q = 1 Pulse generator causes a 1 Q-state pulse width. Name denotes the connection point at the comparator output.
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TABLE 17-1:
SRCLK 111 110 101 100 011 010 001 000
SRCLK FREQUENCY TABLE
Divider 512 256 128 64 32 16 8 4 FOSC = 32 MHz 62.5 kHz 125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz FOSC = 20 MHz 39.0 kHz 78.1 kHz 156 kHz 313 kHz 625 kHz 1.25 MHz 2.5 MHz 5 MHz FOSC = 16 MHz 31.3 kHz 62.5 kHz 125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz FOSC = 4 MHz 7.81 kHz 15.6 kHz 31.25 kHz 62.5 kHz 125 kHz 250 kHz 500 kHz 1 MHz FOSC = 1 MHz 1.95 kHz 3.90 kHz 7.81 kHz 15.6 kHz 31.3 kHz 62.5 kHz 125 kHz 250 kHz
REGISTER 17-1:
R/W-0/0 SRLEN bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7
SRCON0: SR LATCH CONTROL 0 REGISTER
R/W-0/0 SRCLK<2:0> R/W-0/0 R/W-0/0 SRQEN R/W-0/0 SRNQEN R/S-0/0 SRPS R/S-0/0 SRPR bit 0
R/W-0/0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets S = Bit is set only
SRLEN: SR Latch Enable bit 1 = SR latch is enabled 0 = SR latch is disabled SRCLK<2:0>: SR Latch Clock Divider bits 000 = Generates a 1 FOSC wide pulse every 4th FOSC cycle clock 001 = Generates a 1 FOSC wide pulse every 8th FOSC cycle clock 010 = Generates a 1 FOSC wide pulse every 16th FOSC cycle clock 011 = Generates a 1 FOSC wide pulse every 32nd FOSC cycle clock 100 = Generates a 1 FOSC wide pulse every 64th FOSC cycle clock 101 = Generates a 1 FOSC wide pulse every 128th FOSC cycle clock 110 = Generates a 1 FOSC wide pulse every 256th FOSC cycle clock 111 = Generates a 1 FOSC wide pulse every 512th FOSC cycle clock SRQEN: SR Latch Q Output Enable bit If SRLEN = 1: 1 = Q is present on the SRQ pin 0 = External Q output is disabled If SRLEN = 0: SR latch is disabled SRNQEN: SR Latch Q Output Enable bit If SRLEN = 1: 1 = Q is present on the SRnQ pin 0 = External Q output is disabled If SRLEN = 0: SR latch is disabled SRPS: Pulse Set Input of the SR Latch bit(1) 1 = Pulse set input for 1 Q-clock period 0 = No effect on set input. SRPR: Pulse Reset Input of the SR Latch bit(1) 1 = Pulse Reset input for 1 Q-clock period 0 = No effect on Reset input. Set only, always reads back `0'.
bit 6-4
bit 3
bit 2
bit 1
bit 0
Note 1:
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REGISTER 17-2:
R/W-0/0 SRSPE bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared SRSPE: SR Latch Peripheral Set Enable bit 1 = SR latch is set when the SRI pin is high. 0 = SRI pin has no effect on the set input of the SR latch SRSCKE: SR Latch Set Clock Enable bit 1 = Set input of SR latch is pulsed with SRCLK 0 = SRCLK has no effect on the set input of the SR latch SRSC2E: SR Latch C2 Set Enable bit 1 = SR latch is set when the C2 Comparator output is high 0 = C2 Comparator output has no effect on the set input of the SR latch SRSC1E: SR Latch C1 Set Enable bit 1 = SR latch is set when the C1 Comparator output is high 0 = C1 Comparator output has no effect on the set input of the SR latch SRRPE: SR Latch Peripheral Reset Enable bit 1 = SR latch is reset when the SRI pin is high. 0 = SRI pin has no effect on the Reset input of the SR latch SRRCKE: SR Latch Reset Clock Enable bit 1 = Reset input of SR latch is pulsed with SRCLK 0 = SRCLK has no effect on the Reset input of the SR latch SRRC2E: SR Latch C2 Reset Enable bit 1 = SR latch is reset when the C2 Comparator output is high 0 = C2 Comparator output has no effect on the Reset input of the SR latch SRRC1E: SR Latch C1 Reset Enable bit 1 = SR latch is reset when the C1 Comparator output is high 0 = C1 Comparator output has no effect on the Reset input of the SR latch U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
SRCON1: SR LATCH CONTROL 1 REGISTER
R/W-0/0 SRSC2E R/W-0/0 SRSC1E R/W-0/0 SRRPE R/W-0/0 SRRCKE R/W-0/0 SRRC2E R/W-0/0 SRRC1E bit 0
R/W-0/0 SRSCKE
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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TABLE 17-2:
Name ANSELA SRCON0 SRCON1 TRISA
SUMMARY OF REGISTERS ASSOCIATED WITH SR LATCH MODULE
Bit 7 -- SRLEN SRSPE TRISA7 Bit 6 -- SRCLK2 SRSCKE TRISA6 Bit 5 -- SRCLK1 SRSC2E TRISA5 Bit 4 ANSA4 SRCLK0 SRSC1E TRISA4 Bit 3 ANSA3 SRQEN SRRPE TRISA3 Bit 2 ANSA2 SRNQEN TRISA2 Bit 1 ANSA1 SRPS TRISA1 Bit 0 ANSA0 SRPR SRRC1E TRISA0 Register on Page 125 161 162 124
SRRCKE SRRC2E
Legend: -- = unimplemented, read as `0'. Shaded cells are unused by the SR latch module.
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18.0 COMPARATOR MODULE
FIGURE 18-1:
VIN+ VIN-
SINGLE COMPARATOR
+ - Output
Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution. The analog comparator module includes the following features: * * * * * * * * * Independent comparator control Programmable input selection Comparator output is available internally/externally Programmable output polarity Interrupt-on-change Wake-up from Sleep Programmable Speed/Power optimization PWM shutdown Programmable and fixed voltage reference
VINVIN+
Output
Note:
18.1
Comparator Overview
The black areas of the output of the comparator represents the uncertainty due to input offsets and response time.
A single comparator is shown in Figure 18-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level.
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FIGURE 18-2:
CxNCH<1:0> 2 C12IN0C12IN1C12IN2C12IN30 1 MUX 2 (2) 3 CXPOL CxVN
COMPARATOR 1 MODULE SIMPLIFIED BLOCK DIAGRAM
CxON(1)
Interrupt det
CxINTP
Set CxIF
Interrupt det
CxINTN
Cx(3) D Q
CXOUT MCXOUT
To Data Bus
CxVP C1IN+ DAC FVR Buffer2 C12IN+ 0 MUX 1 (2) 2 3
+
Q1 CxHYS CxSP To ECCP PWM Logic EN
CxON CXPCH<1:0> 2 D (from Timer1) T1CLK Note 1: 2: 3: When CxON = 0, the Comparator will produce a `0' at the output When CxON = 0, all multiplexer inputs are disconnected. Output of comparator can be frozen during debugging. Q
CXSYNC
CXOE
TRIS bit CXOUT
0 1
To Timer1 or SR Latch SYNCCXOUT
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FIGURE 18-3:
CxNCH<1:0> 2 C12IN0C12IN1C12IN2C12IN30 1 MUX 2 (2) 3 CXPOL CxVN
COMPARATOR 2 MODULE SIMPLIFIED BLOCK DIAGRAM
CxON(1)
Interrupt det
CxINTP
Set CxIF
Interrupt det
CxINTN
Cx(3) D Q
CXOUT MCXOUT
To Data Bus
CxVP C12IN+ DAC FVR Buffer2 0 MUX 1 (2) 2 3 VSS CXPCH<1:0> 2
+
Q1 CxHYS CxSP To ECCP PWM Logic EN
CxON
CXSYNC
CXOE
TRIS bit CXOUT
0 D (from Timer1) T1CLK Q 1
To Timer1 or SR Latch SYNCCXOUT
Note
1: 2: 3:
When CxON = 0, the Comparator will produce a `0' at the output When CxON = 0, all multiplexer inputs are disconnected. Output of comparator can be frozen during debugging.
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18.2 Comparator Control
18.2.3 COMPARATOR OUTPUT POLARITY
Each comparator has 2 control registers: CMxCON0 and CMxCON1. The CMxCON0 registers (see Register 18-1) contain Control and Status bits for the following: * * * * * * Enable Output selection Output polarity Speed/Power selection Hysteresis enable Output synchronization Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CxPOL bit of the CMxCON0 register. Clearing the CxPOL bit results in a non-inverted output. Table 18-1 shows the output state versus input conditions, including polarity control.
TABLE 18-1:
COMPARATOR OUTPUT STATE VS. INPUT CONDITIONS
CxPOL 0 0 1 1 CxOUT 0 1 0 1
Input Condition CxVN > CxVP CxVN < CxVP CxVN > CxVP CxVN < CxVP
The CMxCON1 registers (see Register 18-2) contain Control bits for the following: * * * * Interrupt enable Interrupt edge polarity Positive input channel selection Negative input channel selection
18.2.4
18.2.1
COMPARATOR ENABLE
COMPARATOR SPEED/POWER SELECTION
Setting the CxON bit of the CMxCON0 register enables the comparator for operation. Clearing the CxON bit disables the comparator resulting in minimum current consumption.
18.2.2
COMPARATOR OUTPUT SELECTION
The trade-off between speed or power can be optimized during program execution with the CxSP control bit. The default state for this bit is `1' which selects the normal speed mode. Device power consumption can be optimized at the cost of slower comparator propagation delay by clearing the CxSP bit to `0'.
The output of the comparator can be monitored by reading either the CxOUT bit of the CMxCON0 register or the MCxOUT bit of the CMOUT register. In order to make the output available for an external connection, the following conditions must be true: * CxOE bit of the CMxCON0 register must be set * Corresponding TRIS bit must be cleared * CxON bit of the CMxCON0 register must be set Note 1: The CxOE bit of the CMxCON0 register overrides the PORT data latch. Setting the CxON bit of the CMxCON0 register has no impact on the port override. 2: The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched.
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18.3 Comparator Hysteresis 18.5 Comparator Interrupt
A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the CxHYS bit of the CMxCON0 register. See Section 29.0 "Electrical Specifications" for more information. An interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a Falling edge detector are present. When either edge detector is triggered and its associated enable bit is set (CxINTP and/or CxINTN bits of the CMxCON1 register), the Corresponding Interrupt Flag bit (CxIF bit of the PIR2 register) will be set. To enable the interrupt, you must set the following bits: * CxON, CxPOL and CxSP bits of the CMxCON0 register * CxIE bit of the PIE2 register * CxINTP bit of the CMxCON1 register (for a rising edge detection) * CxINTN bit of the CMxCON1 register (for a falling edge detection) * PEIE and GIE bits of the INTCON register The associated interrupt flag bit, CxIF bit of the PIR2 register, must be cleared in software. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. Note: Although a comparator is disabled, an interrupt can be generated by changing the output polarity with the CxPOL bit of the CMxCON0 register, or by switching the comparator on or off with the CxON bit of the CMxCON0 register.
18.4
Timer1 Gate Operation
The output resulting from a comparator operation can be used as a source for gate control of Timer1. See Section 20.6 "Timer1 Gate" for more information. This feature is useful for timing the duration or interval of an analog event. It is recommended that the comparator output be synchronized to Timer1. This ensures that Timer1 does not increment while a change in the comparator is occurring.
18.4.1
COMPARATOR OUTPUT SYNCHRONIZATION
The output from either comparator, C1 or C2, can be synchronized with Timer1 by setting the CxSYNC bit of the CMxCON0 register. Once enabled, the comparator output is latched on the falling edge of the Timer1 source clock. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator Block Diagram (Figure 18-2) and the Timer1 Block Diagram (Figure 20-1) for more information.
18.6
Comparator Positive Input Selection
Configuring the CxPCH<1:0> bits of the CMxCON1 register directs an internal voltage reference or an analog pin to the non-inverting input of the comparator: * * * * C1IN+ or C2IN+ analog pin DAC FVR (Fixed Voltage Reference) VSS (Ground)
See Section 14.0 "Fixed Voltage Reference (FVR)" for more information on the Fixed Voltage Reference module. See Section 16.0 "Digital-to-Analog Converter (DAC) Module" for more information on the DAC input signal. Any time the comparator is disabled (CxON = 0), all comparator inputs are disabled.
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18.7 Comparator Negative Input Selection 18.10 Analog Input Connection Considerations
A simplified circuit for an analog input is shown in Figure 18-1. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced. Note 1: When reading a PORT register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert as an analog input, according to the input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified.
The CxNCH<1:0> bits of the CMxCON0 register direct one of four analog pins to the comparator inverting input. Note: To use CxIN+ and CxINx- pins as analog input, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers.
18.8
Comparator Response Time
The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input change. See the Comparator and Voltage Reference Specifications in Section 29.0 "Electrical Specifications" for more details.
18.9
Interaction with ECCP Logic
The C1 and C2 comparators can be used as general purpose comparators. Their outputs can be brought out to the C1OUT and C2OUT pins. When the ECCP Auto-Shutdown is active it can use one or both comparator signals. If auto-restart is also enabled, the comparators can be configured as a closed loop analog feedback to the ECCP, thereby, creating an analog controlled PWM. Note: When the Comparator module is first initialized the output state is unknown. Upon initialization, the user should verify the output state of the comparator prior to relying on the result, primarily when using the result in connection with other peripheral features, such as the ECCP Auto-Shutdown mode.
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FIGURE 18-4: ANALOG INPUT MODEL
VDD Rs < 10K Analog Input pin VT 0.6V RIC To Comparator VA CPIN 5 pF VT 0.6V ILEAKAGE(1)
Vss Legend: CPIN = Input Capacitance ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Source Impedance RS VA = Analog Voltage = Threshold Voltage VT
Note 1: See Section 29.0 "Electrical Specifications"
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REGISTER 18-1:
R/W-0/0 CxON bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared CxON: Comparator Enable bit 1 = Comparator is enabled and consumes no active power 0 = Comparator is disabled CxOUT: Comparator Output bit If CxPOL = 1 (inverted polarity): 1 = CxVP < CxVN 0 = CxVP > CxVN If CxPOL = 0 (non-inverted polarity): 1 = CxVP > CxVN 0 = CxVP < CxVN CxOE: Comparator Output Enable bit 1 = CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually drive the pin. Not affected by CxON. 0 = CxOUT is internal only CxPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted Unimplemented: Read as `0' CxSP: Comparator Speed/Power Select bit 1 = Comparator operates in normal power, higher speed mode 0 = Comparator operates in low-power, low-speed mode CxHYS: Comparator Hysteresis Enable bit 1 = Comparator hysteresis enabled 0 = Comparator hysteresis disabled CxSYNC: Comparator Output Synchronous Mode bit 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source. 0 = Comparator output to Timer1 and I/O pin is asynchronous. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
CMxCON0: COMPARATOR Cx CONTROL REGISTER 0
R-0/0 R/W-0/0 CxOE R/W-0/0 CxPOL U-0 -- R/W-1/1 CxSP R/W-0/0 CxHYS R/W-0/0 CxSYNC bit 0
CxOUT
bit 6
bit 5
bit 4
bit 3 bit 2
bit 1
bit 0
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REGISTER 18-2:
R/W-0/0 CxINTP bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit 0 = No interrupt flag will be set on a positive going edge of the CxOUT bit CxINTN: Comparator Interrupt on Negative Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit 0 = No interrupt flag will be set on a negative going edge of the CxOUT bit CxPCH<1:0>: Comparator Positive Input Channel Select bits 00 = CxVP connects to CxIN+ pin 01 = CxVP connects to DAC Voltage Reference 10 = CxVP connects to FVR Voltage Reference For C1: 11 = CxVP connects to C12IN+ pin For C2: 11 = CxVP connects to VSS Unimplemented: Read as `0' CxNCH<1:0>: Comparator Negative Input Channel Select bits 00 = CxVN connects to C12IN0- pin 01 = CxVN connects to C12IN1- pin 10 = CxVN connects to C12IN2- pin 11 = CxVN connects to C12IN3- pin U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
CMxCON1: COMPARATOR Cx CONTROL REGISTER 1
R/W-0/0 R/W-0/0 U-0 -- U-0 -- R/W-0/0 R/W-0/0 bit 0 CxPCH<1:0> CxNCH<1:0>
R/W-0/0 CxINTN
bit 6
bit 5-4
bit 3-2 bit 1-0
REGISTER 18-3:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-2 bit 1 bit 0
CMOUT: COMPARATOR OUTPUT REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R-0/0 MC2OUT R-0/0 MC1OUT bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
Unimplemented: Read as `0' MC2OUT: Mirror Copy of C2OUT bit MC1OUT: Mirror Copy of C1OUT bit
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TABLE 18-2:
Name ANSELA CMxCON0 CMxCON1 CMOUT DACCON0 DACCON1 FVRCON INTCON LATA PIE2 PIR2 PORTA TRISA Legend: Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Bit 7 -- CxON CxNTP -- DACEN -- FVREN GIE LATA7 OSFIE OSFIF RA7 TRISA7 Bit 6 -- CxOUT CxINTN -- DACLPS -- FVRRDY PEIE LATA6 C2IE C2IF RA6 TRISA6 Bit 5 -- CxOE CxPCH1 -- DACOE -- Reserved TMR0IE -- C1IE C1IF RA5 TRISA5 Bit 4 ANSA4 CxPOL CxPCH0 -- -- DACR4 Reserved INTE LATA4 EEIE EEIF RA4 TRISA4 Bit 3 ANSA3 -- -- -- DACPSS1 DACR3 CDAFVR1 IOCIE LATA3 BCL1IE BCL1IF RA3 TRISA3 Bit 2 ANSA2 CxSP -- -- DACPSS0 DACR2 CDAFVR0 TMR0IF LATA2 -- -- RA2 TRISA2 Bit 1 ANSA1 CxHYS CxNCH1 MC2OUT -- DACR1 ADFVR1 INTF LATA1 -- -- RA1 TRISA1 Bit 0 ANSA0 CxSYNC CxNCH0 MC1OUT DACNSS DACR0 ADFVR0 IOCIF LATA0 CCP2IE(1) CCP2IF(1) RA0 TRISA0 Register on Page 125 172 173 173 157 157 138 91 124 93 97 124 124
-- = unimplemented, read as `0'. Shaded cells are unused by the Comparator module. PIC16F/LF1827 only.
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19.0 TIMER0 MODULE
19.1.2 8-BIT COUNTER MODE
The Timer0 module is an 8-bit timer/counter with the following features: * * * * * * 8-bit timer/counter register (TMR0) 8-bit prescaler (independent of Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow TMR0 can be used to gate Timer1 In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin or the Capacitive Sensing Oscillator (CPSCLK) signal. 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION register to `1' and resetting the T0XCS bit in the CPSCON0 register to `0'. 8-Bit Counter mode using the Capacitive Sensing Oscillator (CPSCLK) signal is selected by setting the TMR0CS bit in the OPTION register to `1' and setting the T0XCS bit in the CPSCON0 register to `1'. The rising or falling transition of the incrementing edge for either input source is determined by the TMR0SE bit in the OPTION register.
Figure 19-1 is a block diagram of the Timer0 module.
19.1
Timer0 Operation
The Timer0 module can be used as either an 8-bit timer or an 8-bit counter.
19.1.1
8-BIT TIMER MODE
The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-Bit Timer mode is selected by clearing the TMR0CS bit of the OPTION register. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written.
FIGURE 19-1:
FOSC/4
BLOCK DIAGRAM OF THE TIMER0
Data Bus 0 T0CKI 0 From CPSCLK 1 0 1 TMR0SE TMR0CS 8-bit Prescaler PSA Set Flag bit TMR0IF on Overflow Overflow to Timer1 1 Sync 2 TCY 8 TMR0
T0XCS
8
PS<2:0>
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19.1.3 SOFTWARE PROGRAMMABLE PRESCALER
A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION register. Note: The Watchdog Timer (WDT) uses its own independent prescaler.
There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be disabled by setting the PSA bit of the OPTION register. The prescaler is not readable or writable. All instructions writing to the TMR0 register will clear the prescaler.
19.1.4
TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The TMR0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The TMR0IF bit can only be cleared in software. The Timer0 interrupt enable is the TMR0IE bit of the INTCON register. Note: The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. 8-BIT COUNTER MODE SYNCHRONIZATION
19.1.5
When in 8-Bit Counter mode, the incrementing edge on the T0CKI pin must be synchronized to the instruction clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in Section 29.0 "Electrical Specifications".
19.1.6
OPERATION DURING SLEEP
Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode.
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REGISTER 19-1:
R/W-1/1 WPUEN bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared WPUEN: Weak Pull-up Enable bit 1 = All weak pull-ups are disabled (except MCLR, if it is enabled) 0 = Weak pull-ups are enabled by individual WPUx latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin TMR0CS: Timer0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) TMR0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is not assigned to the Timer0 module 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 Timer0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256
OPTION_REG: OPTION REGISTER
R/W-1/1 TMR0CS R/W-1/1 TMR0SE R/W-1/1 PSA R/W-1/1 R/W-1/1 PS<2:0> bit 0 R/W-1/1
R/W-1/1 INTEDG
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
bit 6
bit 5
bit 4
bit 3
bit 2-0
TABLE 19-1:
Name CPSCON0 INTCON TMR0 TRISA
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Bit 7 CPSON GIE Bit 6 -- PEIE Bit 5 -- TMR0IE Bit 4 -- INTE Bit 3 Bit 2 Bit 1 Bit 0 T0XCS IOCIF PS0 TRISA0 Register on Page 320 91 177 175* TRISA4 TRISA3 TRISA2 TRISA1 124
CPSRNG1 CPSRNG0 CPSOUT IOCIE PSA TMR0IF PS2 INTF PS1
OPTION_REG WPUEN TRISA7
INTEDG TMR0CS TMR0SE TRISA6 TRISA5
Timer0 Module Register
Legend: -- = Unimplemented locations, read as `0'. Shaded cells are not used by the Timer0 module. * Page provides register information.
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20.0 TIMER1 MODULE WITH GATE CONTROL
* * * * Gate Toggle Mode Gate Single-pulse Mode Gate Value Status Gate Event Interrupt
The Timer1 module is a 16-bit timer/counter with the following features: 16-bit timer/counter register pair (TMR1H:TMR1L) Programmable internal or external clock source 2-bit prescaler Dedicated 32 kHz oscillator circuit Optionally synchronized comparator out Multiple Timer1 gate (count enable) sources Interrupt on overflow Wake-up on overflow (external clock, Asynchronous mode only) * Time base for the Capture/Compare function * Special Event Trigger (with CCP/ECCP) * Selectable Gate Source Polarity * * * * * * * *
Figure 20-1 is a block diagram of the Timer1 module.
FIGURE 20-1:
T1GSS<1:0> T1G
TIMER1 BLOCK DIAGRAM
00 01 10 D 11 TMR1ON T1GPOL Set flag bit TMR1IF on Overflow T1GTM CK R Q Q 1 T1G_IN
T1GSPM 0 0 Single Pulse Acq. Control T1GGO/DONE 1 Data Bus D EN Q RD T1GCON Set TMR1GIF
From Timer0 Overflow Comparator 1 SYNCC1OUT Comparator 2 SYNCC2OUT
T1GVAL Q1
Interrupt det TMR1GE TMR1ON
TMR1(2) TMR1H TMR1L Q
To Comparator Module EN D T1CLK 0 1 TMR1CS<1:0> Synchronized clock input
T1OSO
T1SYNC 11 10 Synchronize(3) det
OUT T1OSC 1
Cap. Sensing Oscillator
T1OSI
Prescaler 1, 2, 4, 8 2 T1CKPS<1:0> FOSC/2 Internal Clock
EN 0 FOSC Internal Clock FOSC/4 Internal Clock
01
T1OSCEN
(1)
Sleep input
00
T1CKI To Clock Switching Modules
Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep.
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20.1 Timer1 Operation 20.2 Clock Source Selection
The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source. Timer1 is enabled by configuring the TMR1ON and TMR1GE bits in the T1CON and T1GCON registers, respectively. Table 20-1 displays the Timer1 enable selections. The TMR1CS<1:0> and T1OSCEN bits of the T1CON register are used to select the clock source for Timer1. Table 20-2 displays the clock source selections.
20.2.1
INTERNAL CLOCK SOURCE
When the internal clock source is selected the TMR1H:TMR1L register pair will increment on multiples of FOSC as determined by the Timer1 prescaler. When the FOSC internal clock source is selected, the Timer1 register value will increment by four counts every instruction clock cycle. Due to this condition, a 2 LSB error in resolution will occur when reading the Timer1 value. To utilize the full resolution of Timer1, an asynchronous input signal must be used to gate the Timer1 clock input. The following asynchronous sources may be used: * Asynchronous event on the T1G pin to Timer1 Gate * C1 or C2 comparator input to Timer1 Gate
TABLE 20-1:
TMR1ON 0 0 1 1
TIMER1 ENABLE SELECTIONS
TMR1GE 0 1 0 1 Timer1 Operation Off Off Always On Count Enabled
20.2.2
EXTERNAL CLOCK SOURCE
When the external clock source is selected, the Timer1 module may work as a timer or a counter. When enabled to count, Timer1 is incremented on the rising edge of the external clock input T1CKI or the capacitive sensing oscillator signal. Either of these external clock sources can be synchronized to the microcontroller system clock or they can run asynchronously. When used as a timer with a clock oscillator, an external 32.768 kHz crystal can be used in conjunction with the dedicated internal oscillator circuit. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: * * * * Timer1 enabled after POR Write to TMR1H or TMR1L Timer1 is disabled Timer1 is disabled (TMR1ON = 0) when T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low.
TABLE 20-2:
TMR1CS1 0 0 1 1 1
CLOCK SOURCE SELECTIONS
TMR1CS0 1 0 1 0 0 T1OSCEN x x x 0 1 System Clock (FOSC) Instruction Clock (FOSC/4) Capacitive Sensing Oscillator External Clocking on T1CKI Pin Osc.Circuit On T1OSI/T1OSO Pins Clock Source
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20.3 Timer1 Prescaler 20.6 Timer1 Gate
Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 Gate circuitry. This is also referred to as Timer1 Gate Enable. Timer1 Gate can also be driven by multiple selectable sources.
20.4
Timer1 Oscillator
20.6.1
TIMER1 GATE ENABLE
A dedicated low-power 32.768 kHz oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). This internal circuit is to be used in conjunction with an external 32.768 kHz crystal. The oscillator circuit is enabled by setting the T1OSCEN bit of the T1CON register. The oscillator will continue to run during Sleep. Note: The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1.
The Timer1 Gate Enable mode is enabled by setting the TMR1GE bit of the T1GCON register. The polarity of the Timer1 Gate Enable mode is configured using the T1GPOL bit of the T1GCON register. When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock source. When Timer1 Gate Enable mode is disabled, no incrementing will occur and Timer1 will hold the current count. See Figure 20-3 for timing details.
TABLE 20-3:
T1CLK
TIMER1 GATE ENABLE SELECTIONS
T1G 0 1 0 1 Timer1 Operation Counts Holds Count Holds Count Counts 0 0 1 1
20.5
Timer1 Operation in Asynchronous Counter Mode
T1GPOL
If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer increments asynchronously to the internal phase clocks. If external clock source is selected then the timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 20.5.1 "Reading and Writing Timer1 in Asynchronous Counter Mode"). Note: When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment.
20.6.2
TIMER1 GATE SOURCE SELECTION
The Timer1 Gate source can be selected from one of four different sources. Source selection is controlled by the T1GSS bits of the T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the T1GCON register.
TABLE 20-4:
T1GSS 00 01 10 11
TIMER1 GATE SOURCES
Timer1 Gate Source
Timer1 Gate Pin Overflow of Timer0 (TMR0 increments from FFh to 00h) Comparator 1 Output SYNCC1OUT (optionally Timer1 synchronized output) Comparator 2 Output SYNCC2OUT (optionally Timer1 synchronized output)
20.5.1
READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE
Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair.
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20.6.2.1 T1G Pin Gate Operation 20.6.4
The T1G pin is one source for Timer1 Gate Control. It can be used to supply an external source to the Timer1 Gate circuitry.
TIMER1 GATE SINGLE-PULSE MODE
20.6.2.2
Timer0 Overflow Gate Operation
When Timer0 increments from FFh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 Gate circuitry.
20.6.2.3
Comparator C1 Gate Operation
The output resulting from a Comparator 1 operation can be selected as a source for Timer1 Gate Control. The Comparator 1 output (SYNCC1OUT) can be synchronized to the Timer1 clock or left asynchronous. For more information see Section 18.4.1 "Comparator Output Synchronization".
When Timer1 Gate Single-Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1 Gate Single-Pulse mode is first enabled by setting the T1GSPM bit in the T1GCON register. Next, the T1GGO/DONE bit in the T1GCON register must be set. The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the T1GGO/DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer1 until the T1GGO/DONE bit is once again set in software.See Example 20-5 for timing details. If the Single Pulse Gate mode is disabled by clearing the T1GSPM bit in the T1GCON register, the T1GGO/DONE bit should also be cleared. Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the Timer1 Gate source to be measured. See Figure 20-6 for timing details.
20.6.2.4
Comparator C2 Gate Operation
The output resulting from a Comparator 2 operation can be selected as a source for Timer1 Gate Control. The Comparator 2 output (SYNCC2OUT) can be synchronized to the Timer1 clock or left asynchronous. For more information see Section 18.4.1 "Comparator Output Synchronization".
20.6.5
TIMER1 GATE VALUE STATUS
20.6.3
TIMER1 GATE TOGGLE MODE
When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate signal, as opposed to the duration of a single level pulse. The Timer1 Gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 20-4 for timing details. Timer1 Gate Toggle mode is enabled by setting the T1GTM bit of the T1GCON register. When the T1GTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. Note: Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation.
When Timer1 Gate Value Status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the T1GVAL bit in the T1GCON register. The T1GVAL bit is valid even when the Timer1 Gate is not enabled (TMR1GE bit is cleared).
20.6.6
TIMER1 GATE EVENT INTERRUPT
When Timer1 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of T1GVAL occurs, the TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 Gate is not enabled (TMR1GE bit is cleared).
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20.7 Timer1 Interrupt 20.9
The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: * * * * TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register
ECCP/CCP Capture/Compare Time Base
The CCP modules use the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode. In Capture mode, the value in the TMR1H:TMR1L register pair is copied into the CCPR1H:CCPR1L register pair on a configured event. In Compare mode, an event is triggered when the value CCPR1H:CCPR1L register pair matches the value in the TMR1H:TMR1L register pair. This event can be a Special Event Trigger. For more information, see "Capture/Compare/PWM Modules". Section 23.0
The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. Note: The TMR1H:TMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts.
20.10 ECCP/CCP Special Event Trigger
When any of the CCP's are configured to trigger a special event, the trigger will clear the TMR1H:TMR1L register pair. This special event does not cause a Timer1 interrupt. The CCP module may still be configured to generate a CCP interrupt. In this mode of operation, the CCPR1H:CCPR1L register pair becomes the period register for Timer1. Timer1 should be synchronized and FOSC/4 should be selected as the clock source in order to utilize the Special Event Trigger. Asynchronous operation of Timer1 can cause a Special Event Trigger to be missed. In the event that a write to TMR1H or TMR1L coincides with a Special Event Trigger from the CCP, the write will take precedence. For more information, see Section 15.2.5 "Special Event Trigger".
20.8
Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: * * * * * TMR1ON bit of the T1CON register must be set TMR1IE bit of the PIE1 register must be set PEIE bit of the INTCON register must be set T1SYNC bit of the T1CON register must be set TMR1CS bits of the T1CON register must be configured * T1OSCEN bit of the T1CON register must be configured The device will wake-up on an overflow and execute the next instructions. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine. Timer1 oscillator will continue to operate in Sleep regardless of the T1SYNC bit setting.
FIGURE 20-2:
T1CKI = 1 when TMR1 Enabled
TIMER1 INCREMENTING EDGE
T1CKI = 0 when TMR1 Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
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FIGURE 20-3: TIMER1 GATE ENABLE MODE
TMR1GE T1GPOL T1G_IN
T1CKI
T1GVAL
Timer1
N
N+1
N+2
N+3
N+4
FIGURE 20-4:
TIMER1 GATE TOGGLE MODE
TMR1GE T1GPOL
T1GTM
T1G_IN
T1CKI
T1GVAL
Timer1
N
N+1 N+2 N+3
N+4
N+5 N+6 N+7
N+8
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FIGURE 20-5: TIMER1 GATE SINGLE-PULSE MODE
TMR1GE T1GPOL T1GSPM T1GGO/ DONE T1G_IN Set by software Counting enabled on rising edge of T1G Cleared by hardware on falling edge of T1GVAL
T1CKI
T1GVAL
Timer1
N
N+1
N+2 Set by hardware on falling edge of T1GVAL Cleared by software
TMR1GIF
Cleared by software
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FIGURE 20-6:
TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ DONE T1G_IN Set by software Counting enabled on rising edge of T1G Cleared by hardware on falling edge of T1GVAL
TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
T1CKI
T1GVAL
Timer1
N
N+1
N+2
N+3
N+4 Cleared by software
TMR1GIF
Cleared by software
Set by hardware on falling edge of T1GVAL
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20.11 Timer1 Control Register
The Timer1 Control register (T1CON), shown in Register 21-1, is used to control Timer1 and select the various features of the Timer1 module.
REGISTER 20-1:
R/W-0/u bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6
T1CON: TIMER1 CONTROL REGISTER
R/W-0/u R/W-0/u R/W-0/u T1OSCEN R/W-0/u T1SYNC U-0 -- R/W-0/u TMR1ON bit 0
R/W-0/u
TMR1CS<1:0>
T1CKPS<1:0>
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
TMR1CS<1:0>: Timer1 Clock Source Select bits 11 = Timer1 clock source is Capacitive Sensing Oscillator (CAPOSC) 10 = Timer1 clock source is pin or oscillator: If T1OSCEN = 0: External clock from T1CKI pin (on the rising edge) If T1OSCEN = 1: Crystal oscillator on T1OSI/T1OSO pins 01 = Timer1 clock source is system clock (FOSC) 00 = Timer1 clock source is instruction clock (FOSC/4) T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value T1OSCEN: LP Oscillator Enable Control bit 1 = Dedicated Timer1 oscillator circuit enabled 0 = Dedicated Timer1 oscillator circuit disabled T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS<1:0> = 1X 1 = Do not synchronize external clock input 0 = Synchronize external clock input with system clock (FOSC) TMR1CS<1:0> = 0X This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X.
bit 5-4
bit 3
bit 2
bit 1 bit 0
Unimplemented: Read as `0' TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 Gate flip-flop
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20.12 Timer1 Gate Control Register
The Timer1 Gate Control register (T1GCON), shown in Register 21-2, is used to control Timer1 Gate.
REGISTER 20-2:
R/W-0/u TMR1GE bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7
T1GCON: TIMER1 GATE CONTROL REGISTER
R/W-0/u T1GTM R/W-0/u T1GSPM R/W/HC-0/u T1GGO/ DONE R-x/x T1GVAL R/W-0/u R/W-0/u
R/W-0/u T1GPOL
T1GSS<1:0> bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets HC = Bit is cleared by hardware
TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function T1GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) T1GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled 0 = Timer1 Gate Toggle mode is disabled and toggle flip flop is cleared Timer1 gate flip-flop toggles on every rising edge. T1GSPM: Timer1 Gate Single-Pulse Mode bit 1 = Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 gate Single-Pulse mode is disabled T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single-pulse acquisition has completed or has not been started T1GVAL: Timer1 Gate Current State bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. Unaffected by Timer1 Gate Enable (TMR1GE). T1GSS<1:0>: Timer1 Gate Source Select bits 00 = Timer1 Gate pin 01 = Timer0 overflow output 10 = Comparator 1 optionally synchronized output (SYNCC1OUT) 11 = Comparator 2 optionally synchronized output (SYNCC2OUT)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
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TABLE 20-5:
Name ANSELB CCP1CON INTCON PIE1 PIR1 PORTB TMR1H TMR1L TRISB T1CON T1GCON
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Bit 7 ANSB7 PxM1 GIE Bit 6 ANSB6 PxM0 PEIE ADIE ADIF RB6 Bit 5 ANSB5 DCxB1 TMR0IE RCIE RCIF RB5 Bit 4 ANSB4 DCxB0 INTE TXIE TXIF RB4 Bit 3 ANSB3 CCPxM3 IOCIE SSP1IE SSP1IF RB3 Bit 2 ANSB2 CCPxM2 TMR0IF CCP1IE CCP1IF RB2 Bit 1 ANSB1 CCPxM1 INTF TMR2IE TMR2IF RB1 Bit 0 -- CCPxM0 IOCIF TMR1IE TMR1IF RB0 Register on Page 130 228 91 92 96 129 179* 179* TRISB0 TMR1ON T1GSS0 129 187 188 -- T1GSS1
TMR1GIE TMR1GIF RB7
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register Holding Register for the Least Significant Byte of the 16-bit TMR1 Register TRISB7 TMR1GE TRISB6 T1GPOL TRISB5 T1GTM TRISB4 T1GSPM TRISB3 T1GGO/ DONE TRISB2 T1GVAL TRISB1 TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Timer1 module. * Page provides register information.
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21.0 TIMER2/4/6 MODULES
There are up to three identical Timer2-type modules available. To maintain pre-existing naming conventions, the Timers are called Timer2, Timer4 and Timer6 (also Timer2/4/6). Note: The `x' variable used in this section is used to designate Timer2, Timer4, or Timer6. For example, TxCON references T2CON, T4CON, or T6CON. PRx references PR2, PR4, or PR6.
The Timer2/4/6 modules incorporate the following features: * 8-bit Timer and Period registers (TMRx and PRx, respectively) * Readable and writable (both registers) * Software programmable prescaler (1:1, 1:4, 1:16, and 1:64) * Software programmable postscaler (1:1 to 1:16) * Interrupt on TMRx match with PRx, respectively * Optional use as the shift clock for the MSSPx modules (Timer2 only) See Figure 21-1 for a block diagram of Timer2/4/6.
FIGURE 21-1:
TIMER2/4/6 BLOCK DIAGRAM
TMRx Output Sets Flag bit TMRxIF
FOSC/4
Prescaler 1:1, 1:4, 1:16, 1:64 2 TxCKPS<1:0>
TMRx Comparator
Reset Postscaler 1:1 to 1:16 4 TxOUTPS<3:0>
EQ
PRx
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21.1 Timer2/4/6 Operation 21.3 Timer2/4/6 Output
The clock input to the Timer2/4/6 modules is the system instruction clock (FOSC/4). TMRx increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, TxCKPS<1:0> of the TxCON register. The value of TMRx is compared to that of the Period register, PRx, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output. This signal also resets the value of TMRx to 00h on the next cycle and drives the output counter/postscaler (see Section 21.2 "Timer2/4/6 Interrupt"). The TMRx and PRx registers are both directly readable and writable. The TMRx register is cleared on any device Reset, whereas the PRx register initializes to FFh. Both the prescaler and postscaler counters are cleared on the following events: * * * * * * * * * a write to the TMRx register a write to the TxCON register Power-on Reset (POR) Brown-out Reset (BOR) MCLR Reset Watchdog Timer (WDT) Reset Stack Overflow Reset Stack Underflow Reset RESET Instruction Note: TMRx is not cleared when TxCON is written. The unscaled output of TMRx is available primarily to the CCP modules, where it is used as a time base for operations in PWM mode. Timer2 can be optionally used as the shift clock source for the MSSPx modules operating in SPI mode. Additional information is provided in Section 24.0 "Master Synchronous Serial Port (MSSP1 and MSSP2) Module".
21.4
Timer2/4/6 Operation During Sleep
The Timer2/4/6 timers cannot be operated while the processor is in Sleep mode. The contents of the TMRx and PRx registers will remain unchanged while the processor is in Sleep mode.
21.2
Timer2/4/6 Interrupt
Timer2/4/6 can also generate an optional device interrupt. The Timer2/4/6 output signal (TMRx-to-PRx match) provides the input for the 4-bit counter/postscaler. This counter generates the TMRx match interrupt flag which is latched in TMRxIF of the PIRx register. The interrupt is enabled by setting the TMRx Match Interrupt Enable bit, TMRxIE of the PIEx register. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, TxOUTPS<3:0>, of the TxCON register.
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REGISTER 21-1:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 bit 6-3 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0' TOUTPS<3:0>: Timer Output Postscaler Select bits 0000 = 1:1 Postscaler 0001 = 1:2 Postscaler 0010 = 1:3 Postscaler 0011 = 1:4 Postscaler 0100 = 1:5 Postscaler 0101 = 1:6 Postscaler 0110 = 1:7 Postscaler 0111 = 1:8 Postscaler 1000 = 1:9 Postscaler 1001 = 1:10 Postscaler 1010 = 1:11 Postscaler 1011 = 1:12 Postscaler 1100 = 1:13 Postscaler 1101 = 1:14 Postscaler 1110 = 1:15 Postscaler 1111 = 1:16 Postscaler TMRxON: Timerx On bit 1 = Timerx is on 0 = Timerx is off TxCKPS<1:0>: Timer2-type Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 10 = Prescaler is 16 11 = Prescaler is 64 U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
TXCON: TIMER2/TIMER4/TIMER6 CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMRxON R/W-0/0 R/W-0/0 bit 0 TOUTPS<3:0> TxCKPS<1:0>
R/W-0/0
bit 2
bit 1-0
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TABLE 21-1:
Name INTCON PIE1 PIR1 PIE3(1) PIR3(1) PR2 PR4 PR6 T2CON T4CON T6CON TMR2 TMR4 TMR6 Legend: * Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2/4/6
Bit 7 GIE Bit 6 PEIE ADIE ADIF -- -- Bit 5 TMR0IE RCIE RCIF CCP4IE CCP4IF Bit 4 INTE TXIE TXIF CCP3IE CCP3IF Bit 3 IOCIE SSP1IE SSP1IF TMR6IE TMR6IF Bit 2 TMR0IF CCP1IE CCP1IF -- -- Bit 1 INTF TMR2IE TMR2IF TMR4IE TMR4IF Bit 0 IOCIF TMR1IE TMR1IF -- -- Register on Page 91 92 96 94 98 191* 191* 191* TMR2ON TMR4ON TMR6ON T2CKPS1 T4CKPS1 T6CKPS1 T2CKPS0 T4CKPS0 T6CKPS0 193 193 193 191* 191* 193*
TMR1GIE TMR1GIF -- --
Timer2 Module Period Register Timer4 Module Period Register Timer6 Module Period Register -- -- -- T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0
Holding Register for the 8-bit TMR2 Time Base Holding Register for the 8-bit TMR4 Time Base(1) Holding Register for the 8-bit TMR6 Time Base(1) -- = unimplemented read as `0'. Shaded cells are not used for Timer2 module. Page provides register information. PIC16F/LF1827 only.
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22.0 DATA SIGNAL MODULATOR
The Data Signal Modulator (DSM) is a peripheral which allows the user to mix a data stream, also known as a modulator signal, with a carrier signal to produce a modulated output. Both the carrier and the modulator signals are supplied to the DSM module either internally, from the output of a peripheral, or externally through an input pin. The modulated output signal is generated by performing a logical "AND" operation of both the carrier and modulator signals and then provided to the MDOUT pin. The carrier signal is comprised of two distinct and separate signals. A carrier high (CARH) signal and a carrier low (CARL) signal. During the time in which the modulator (MOD) signal is in a logic high state, the DSM mixes the carrier high signal with the modulator signal. When the modulator signal is in a logic low state, the DSM mixes the carrier low signal with the modulator signal. Using this method, the DSM can generate the following types of Key Modulation schemes: * Frequency-Shift Keying (FSK) * Phase-Shift Keying (PSK) * On-Off Keying (OOK) Additionally, the following features are provided within the DSM module: * * * * * * * Carrier Synchronization Carrier Source Polarity Select Carrier Source Pin Disable Programmable Modulator Data Modulator Source Pin Disable Modulated Output Polarity Select Slew Rate Control
Figure 22-1 shows a Simplified Block Diagram of the Data Signal Modulator peripheral.
FIGURE 22-1:
MDCH<3:0> VSS MDCIN1 MDCIN2 CLKR CCP1 CCP2 CCP3 CCP4 Reserved No Channel Selected MDMS<3:0> MDBIT MDMIN CCP1 CCP2 CCP3 CCP4 Comparator C1 Comparator C2 MSSP1 SDO1 MSSP2 SDO2 EUSART Reserved No Channel Selected
SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR
MDEN EN Data Signal Modulator
0000 0001 0010 0011 0100 0101 CARH 0110 0111 1000 * * 1111
MDCHPOL D SYNC Q 1
0000 0001 0010 0011 0100 0101 0110 MOD 0111 1000 1001 1010 0011 * * 1111 D
0 MDCHSYNC MDOUT MDOPOL MDOE
MDCL<3:0> VSS MDCIN1 MDCIN2 CLKR CCP1 CCP2 CCP3 CCP4 Reserved No Channel Selected 0000 0001 0010 0011 0100 0101 CARL 0110 0111 1000 * * 1111
SYNC Q 1
0 MDCLSYNC
MDCLPOL
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22.1 DSM Operation 22.3 Carrier Signal Sources
The DSM module can be enabled by setting the MDEN bit in the MDCON register. Clearing the MDEN bit in the MDCON register, disables the DSM module by automatically switching the carrier high and carrier low signals to the VSS signal source. The modulator signal source is also switched to the MDBIT in the MDCON register. This not only assures that the DSM module is inactive, but that it is also consuming the least amount of current. The values used to select the carrier high, carrier low, and modulator sources held by the Modulation Source, Modulation High Carrier, and Modulation Low Carrier control registers are not affected when the MDEN bit is cleared and the DSM module is disabled. The values inside these registers remain unchanged while the DSM is inactive. The sources for the carrier high, carrier low and modulator signals will once again be selected when the MDEN bit is set and the DSM module is again enabled and active. The modulated output signal can be disabled without shutting down the DSM module. The DSM module will remain active and continue to mix signals, but the output value will not be sent to the MDOUT pin. During the time that the output is disabled, the MDOUT pin will remain low. The modulated output can be disabled by clearing the MDOE bit in the MDCON register. The carrier high signal and carrier low signal can be supplied from the following sources: * * * * * * * * CCP1 Signal CCP2 Signal CCP3 Signal CCP4 Signal Reference Clock Module Signal External Signal on MDCIN1 pin External Signal on MDCIN2 pin VSS
The carrier high signal is selected by configuring the MDCH <3:0> bits in the MDCARH register. The carrier low signal is selected by configuring the MDCL <3:0> bits in the MDCARL register.
22.4
Carrier Synchronization
During the time when the DSM switches between carrier high and carrier low signal sources, the carrier data in the modulated output signal can become truncated. To prevent this, the carrier signal can be synchronized to the modulator signal. When synchronization is enabled, the carrier pulse that is being mixed at the time of the transition is allowed to transition low before the DSM switches over to the next carrier source. Synchronization is enabled separately for the carrier high and carrier low signal sources. Synchronization for the carrier high signal can be enabled by setting the MDCHSYNC bit in the MDCARH register. Synchronization for the carrier low signal can be enabled by setting the MDCLSYNC bit in the MDCARL register. Figure 22-1 through Figure 22-5 show timing diagrams of using various synchronization methods.
22.2
Modulator Signal Sources
The modulator signal can be supplied from the following sources: * * * * * * * * * * * CCP1 Signal CCP2 Signal CCP3 Signal CCP4 Signal MSSP1 SDO1 Signal (SPI Mode Only) MSSP2 SDO2 Signal (SPI Mode Only) Comparator C1 Signal Comparator C2 Signal EUSART TX Signal External Signal on MDMIN1 pin MDBIT bit in the MDCON register
The modulator signal is selected by configuring the MDMS <3:0> bits in the MDSRC register.
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FIGURE 22-2:
Carrier Low (CARL) Carrier High (CARH) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 MDCHSYNC = 1 MDCLSYNC = 1 MDCHSYNC = 0 MDCLSYNC = 0 MDCHSYNC = 0 MDCLSYNC = 1
ON OFF KEYING (OOK) SYNCHRONIZATION
EXAMPLE 22-1:
Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 0 MDCLSYNC = 0 Active Carrier State
NO SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 0)
CARH
CARL
CARH
CARL
FIGURE 22-3:
Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 Active Carrier State
CARRIER HIGH SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 0)
CARH
both
CARL
CARH
both
CARL
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FIGURE 22-4:
Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 0 MDCLSYNC = 1 Active Carrier State CARH CARL CARH CARL
CARRIER LOW SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 1)
FIGURE 22-5:
Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 1 Active Carrier State
FULL SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 1)
Falling edges used to sync
CARH
CARL
CARH
CARL
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22.5 CARRIER SOURCE POLARITY SELECT 22.12 Effects of a Reset
Upon any device Reset, the Data Signal Modulator module is disabled. The user's firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values.
The signal provided from any selected input source for the carrier high and carrier low signals can be inverted. Inverting the signal for the carrier high source is enabled by setting the MDCHPOL bit of the MDCARH register. Inverting the signal for the carrier low source is enabled by setting the MDCLPOL bit of the MDCARL register.
22.6
CARRIER SOURCE PIN DISABLE
Some peripherals assert control over their corresponding output pin when they are enabled. For example, when the CCP1 module is enabled, the output of CCP1 is connected to the CCP1 pin. This default connection to a pin can be disabled by setting the MDCHODIS bit in the MDCARH register for the carrier high source and the MDCLODIS bit in the MDCARL register for the carrier low source.
22.7
PROGRAMMABLE MODULATOR DATA
The MDBIT of the MDCON register can be selected as the source for the modulator signal. This gives the user the ability to program the value used for modulation.
22.8
MODULATOR SOURCE PIN DISABLE
The modulator source default connection to a pin can be disabled by setting the MDMSODIS bit in the MDSRC register.
22.9
MODULATED OUTPUT POLARITY
The modulated output signal provided on the MDOUT pin can also be inverted. Inverting the modulated output signal is enabled by setting the MDOPOL bit of the MDCON register.
22.10 SLEW RATE CONTROL
The slew rate limitation on the output port pin can be disabled. The slew rate limitation can be removed by clearing the MDSLR bit in the MDCON register.
22.11 OPERATION IN SLEEP MODE
The DSM module is not affected by Sleep mode. The DSM can still operate during Sleep, if the Carrier and Modulator input sources are also still operable during Sleep.
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REGISTER 22-1:
R/W-0/0 MDEN bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared MDEN: Modulator Module Enable bit 1 = Modulator module is enabled and mixing input signals 0 = Modulator module is disabled and has no output MDOE: Modulator Module Pin Output Enable bit 1 = Modulator pin output enabled 0 = Modulator pin output disabled MDSLR: MDOUT Pin Slew Rate Limiting bit 1 = MDOUT pin slew rate limiting enabled 0 = MDOUT pin slew rate limiting disabled MDOPOL: Modulator Output Polarity Select bit 1 = Modulator output signal is inverted 0 = Modulator output signal is not inverted MDOUT: Modulator Output bit Displays the current output value of the Modulator module.(1) Unimplemented: Read as `0' MDBIT: Allows software to manually set modulation source input to module(2) The modulated output frequency can be greater and asynchronous from the clock that updates this register bit, the bit value may not be valid for higher speed modulator or carrier signals. MDBIT must be selected as the modulation source in the MDSRC register for this operation. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
MDCON: MODULATION CONTROL REGISTER
R/W-1/1 MDSLR R/W-0/0 MDOPOL R-0/0 MDOUT U-0 -- U-0 -- R/W-0/0 MDBIT bit 0 MDOE
R/W-0/0
bit 6
bit 5
bit 4
bit 3 bit 2-1 bit 0 Note 1: 2:
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REGISTER 22-2:
R/W-x/u MDMSODIS bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared MDMSODIS: Modulation Source Output Disable 1 = Output signal driving the peripheral output pin (selected by MDMS<3:0>) is disabled 0 = Output signal driving the peripheral output pin (selected by MDMS<3:0>) is enabled Unimplemented: Read as `0' MDMS<3:0> Modulation Source Selection bits 1111 = Reserved. No channel connected. 1110 = Reserved. No channel connected. 1101 = Reserved. No channel connected. 1100 = Reserved. No channel connected. 1011 = Reserved. No channel connected. 1010 = EUSART TX output 1001 = MSSP2 SDOx output 1000 = MSSP1 SDOx output 0111 = Comparator2 output 0110 = Comparator1 output 0101 = CCP4 output (PWM Output mode only) 0100 = CCP3 output (PWM Output mode only) 0011 = CCP2 output (PWM Output mode only) 0010 = CCP1 output (PWM Output mode only) 0001 = MDMIN port pin 0000 = MDBIT bit of MDCON register is modulation source Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
MDSRC: MODULATION SOURCE CONTROL REGISTER
U-0 -- U-0 -- U-0 -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u bit 0 MDMS<3:0>
bit 6-4 bit 3-0
Note 1:
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REGISTER 22-3:
R/W-x/u MDCHODIS bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared MDCHODIS: Modulator High Carrier Output Disable 1 = Output signal driving the peripheral output pin (selected by MDCH<3:0>) is disabled 0 = Output signal driving the peripheral output pin (selected by MDCH<3:0>) is enabled MDCHPOL: Modulator High Carrier Polarity Select bit 1 = Selected high carrier signal is inverted 0 = Selected high carrier signal is not inverted MDCHSYNC: Modulator High Carrier Synchronization Enable bit 1 = Modulator waits for a falling edge on the high time carrier signal before allowing a switch to the low time carrier 0 = Modulator Output is not synchronized to the high time carrier signal(1) Unimplemented: Read as `0' MDCH<3:0> Modulator Data High Carrier Selection bits (1) 1111 = Reserved. No channel connected. * * * 1000 = Reserved. No channel connected. 0111 = CCP4 output (PWM Output mode only) 0110 = CCP3 output (PWM Output mode only) 0101 = CCP2 output (PWM Output mode only) 0100 = CCP1 output (PWM Output mode only) 0011 = Reference Clock module signal 0010 = MDCIN2 port pin 0001 = MDCIN1 port pin 0000 = VSS Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
MDCARH: MODULATION HIGH CARRIER CONTROL REGISTER
R/W-x/u MDCHSYNC U-0 -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u bit 0 MDCH<3:0>
R/W-x/u MDCHPOL
bit 6
bit 5
bit 4 bit 3-0
Note 1:
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REGISTER 22-4:
R/W-x/u MDCLODIS bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared MDCLODIS: Modulator Low Carrier Output Disable 1 = Output signal driving the peripheral output pin (selected by MDCL<3:0> of the MDCARL register) is disabled 0 = Output signal driving the peripheral output pin (selected by MDCL<3:0> of the MDCARL register) is enabled MDCLPOL: Modulator Low Carrier Polarity Select bit 1 = Selected low carrier signal is inverted 0 = Selected low carrier signal is not inverted MDCLSYNC: Modulator Low Carrier Synchronization Enable bit 1 = Modulator waits for a falling edge on the low time carrier signal before allowing a switch to the high time carrier 0 = Modulator Output is not synchronized to the low time carrier signal(1) Unimplemented: Read as `0' MDCL<3:0> Modulator Data High Carrier Selection bits (1) 1111 = Reserved. No channel connected. * * * 1000 = Reserved. No channel connected. 0111 = CCP4 output (PWM Output mode only) 0110 = CCP3 output (PWM Output mode only) 0101 = CCP2 output (PWM Output mode only) 0100 = CCP1 output (PWM Output mode only) 0011 = Reference Clock module signal 0010 = MDCIN2 port pin 0001 = MDCIN1 port pin 0000 = VSS Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
MDCARL: MODULATION LOW CARRIER CONTROL REGISTER
R/W-x/u MDCLSYNC U-0 -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u bit 0 MDCL<3:0>
R/W-x/u MDCLPOL
bit 6
bit 5
bit 4 bit 3-0
Note 1:
TABLE 22-1:
Name MDCARH MDCARL MDCON MDSRC Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH DATA SIGNAL MODULATOR MODE
Bit 7 Bit 6 MDCHPOL MDCLPOL MDOE -- Bit 5 MDCHSYNC MDCLSYNC MDSLR -- Bit 4 -- -- MDOPOL -- MDOUT Bit 3 Bit 2 Bit 1 Bit 0 Register on Page 202 203 MDBIT 200 201
MDCHODIS MDCLODIS MDEN MDMSODIS
MDCH<3:0> MDCL<3:0> -- -- MDMS<3:0>
-- = unimplemented, read as `0'. Shaded cells are not used in the Data Signal Modulator mode.
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NOTES:
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23.0 CAPTURE/COMPARE/PWM MODULES
Note 1: In devices with more than one CCP module, it is very important to pay close attention to the register names used. A number placed after the module acronym is used to distinguish between separate modules. For example, the CCP1CON and CCP2CON control the same operational aspects of two completely different CCP modules. 2: Throughout this section, generic references to a CCP module in any of its operating modes may be interpreted as being equally applicable to ECCP1, ECCP2, CCP3 and CCP4. Register names, module signals, I/O pins, and bit names may use the generic designator 'x' to indicate the use of a numeral to distinguish a particular module, when required.
The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle. This family of devices contains two Enhanced Capture/Compare/PWM modules (ECCP1 and ECCP2,) and two standard Capture/Compare/PWM modules (CCP3 and CCP4). The Capture and Compare functions are identical for all four CCP modules (ECCP1, ECCP2, CCP3, and CCP4). The only differences between CCP modules are in the Pulse-Width Modulation (PWM) function. The standard PWM function is identical in modules, CCP3 and CCP4. In CCP modules ECCP1 and ECCP2, the Enhanced PWM function has slight variations from one another. Full-Bridge ECCP modules have four available I/O pins while Half-Bridge ECCP modules only have two available I/O pins. See Table 23-1 for more information.
TABLE 23-1:
PWM RESOURCES
ECCP1 Enhanced PWM Full-Bridge Enhanced PWM Full-Bridge ECCP2 Not Available Enhanced PWM Half-Bridge CCP3 Not Available Standard PWM CCP4 Not Available Standard PWM
Device Name PIC16F/LF1826 PIC16F/LF1827
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23.1 Capture Mode
23.1.2 TIMER1 MODE RESOURCE
The Capture mode function described in this section is available and identical for CCP modules ECCP1, ECCP2, CCP3 and CCP4. Capture mode makes use of the 16-bit Timer1 resource. When an event occurs on the CCPx pin, the 16-bit CCPRxH:CCPRxL register pair captures and stores the 16-bit value of the TMR1H:TMR1L register pair, respectively. An event is defined as one of the following and is configured by the CCPxM<3:0> bits of the CCPxCON register: * * * * Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. See Section 20.0 "Timer1 Module with Gate Control" for more information on configuring Timer1.
23.1.3
SOFTWARE INTERRUPT MODE
When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit of the PIEx register clear to avoid false interrupts. Additionally, the user should clear the CCPxIF interrupt flag bit of the PIRx register following any change in Operating mode. Note: Clocking Timer1 from the system clock (FOSC) should not be used in Capture mode. In order for Capture mode to recognize the trigger event on the CCPx pin, Timer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source.
When a capture is made, the Interrupt Request Flag bit CCPxIF of the PIRx register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPRxH, CCPRxL register pair is read, the old captured value is overwritten by the new captured value. Figure 23-1 shows a simplified diagram of the Capture operation.
23.1.4
CCP PRESCALER
23.1.1
CCP PIN CONFIGURATION
In Capture mode, the CCPx pin should be configured as an input by setting the associated TRIS control bit. Also, the CCPx pin function can be moved to alternative pins using the APFCON0 or APFCON1 register. Refer to Section 12.1 "Alternate Pin Function" for more details. Note: If the CCPx pin is configured as an output, a write to the port can cause a capture condition.
There are four prescaler settings specified by the CCPxM<3:0> bits of the CCPxCON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCPxCON register before changing the prescaler. Example 12-1 demonstrates the code to perform this function.
FIGURE 23-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
Set Flag bit CCPxIF (PIRx register)
EXAMPLE 23-1:
BANKSEL CCPxCON CLRF MOVLW
CHANGING BETWEEN CAPTURE PRESCALERS
Prescaler 1, 4, 16 CCPx pin
CCPRxH and Edge Detect Capture Enable TMR1H
CCPRxL
MOVWF
;Set Bank bits to point ;to CCPxCON CCPxCON ;Turn CCP module off NEW_CAPT_PS ;Load the W reg with ;the new prescaler ;move value and CCP ON CCPxCON ;Load CCPxCON with this ;value
TMR1L
CCPxM<3:0> System Clock (FOSC)
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23.1.5 CAPTURE DURING SLEEP 23.1.6 ALTERNATE PIN LOCATIONS
Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. When Timer1 is clocked by FOSC/4, Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. Capture mode will operate during Sleep when Timer1 is clocked by an external clock source. This module incorporates I/O pins that can be moved to other locations with the use of the Alternate Pin Function registers, APFCON0 and APFCON1. To determine which pins can be moved and what their default locations are upon a Reset, see Section 12.1 "Alternate Pin Function" for more information.
TABLE 23-2:
Name APFCON0 CCPxCON CCPRxL CCPRxH CMxCON0 CMxCON1 INTCON PIE1 PIE2 PIE3(2) PIR1 PIR2 PIR3
(2)
SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE
Bit 7 Bit 6 Bit 5 SS1SEL DCxB1 Bit 4 P2BSEL(2) DCxB0 Bit 3 CCP2SEL(2) CCPxM3 Bit 2 P1DSEL CCPxM2 Bit 1 P1CSEL CCPxM1 Bit 0 CCP1SEL CCPxM0 Register on Page 122 228 206* 206* -- -- IOCIE SSP1IE BCL1IE TMR6IE SSP1IF BCL1IF TMR6IF T1OSCEN T1GGO/DONE CxSP -- TMR0IF CCP1IE -- -- CCP1IF -- -- T1SYNC T1GVAL CxHYS CxNCH1 INTF TMR2IE -- TMR4IE TMR2IF -- TMR4IF -- T1GSS1 CxSYNC CxNCH0 IOCIF TMR1IE CCP2IE(2) -- TMR1IF CCP2IF(2) -- TMR1ON T1GSS0 172 173 91 92 93 94 96 97 98 187 188 179* 179* TRISA1 TRISB1 TRISA0 TRISB0 124 129
RXDTSEL SDO1SEL PxM1(1) PxM0(1)
Capture/Compare/PWM Register x Low Byte (LSB) Capture/Compare/PWM Register x High Byte (MSB) CxON CxINTP GIE TMR1GIE OSFIE -- TMR1GIF OSFIF -- TMR1GE CxOUT CxINTN PEIE ADIE C2IE -- ADIF C2IF -- T1GPOL CxOE CxPCH1 TMR0IE RCIE C1IE CCP4IE RCIF C1IF CCP4IF T1CKPS1 T1GTM CxPOL CxPCH0 INTE TXIE EEIE CCP3IE TXIF EEIF CCP3IF T1CKPS0 T1GSPM
T1CON T1GCON TMR1L TMR1H TRISA TRISB
TMR1CS1 TMR1CS0
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TRISA7 TRISB7 TRISA6 TRISB6 TRISA5 TRISB5 TRISA4 TRISB4 TRISA3 TRISB3 TRISA2 TRISB2
Legend: -- = Unimplemented locations, read as `0'. Shaded cells are not used by Capture mode. * Page provides register information. Note 1: Applies to ECCP modules only. 2: PIC16F/LF1827 only.
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23.2 Compare Mode
23.2.2 TIMER1 MODE RESOURCE
The Compare mode function described in this section is available and identical for CCP modules ECCP1, ECCP2, CCP3 and CCP4. Compare mode makes use of the 16-bit Timer1 resource. The 16-bit value of the CCPRxH:CCPRxL register pair is constantly compared against the 16-bit value of the TMR1H:TMR1L register pair. When a match occurs, one of the following events can occur: * * * * * Toggle the CCPx output Set the CCPx output Clear the CCPx output Generate a Special Event Trigger Generate a Software Interrupt In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode. See Section 23.2.2 "Timer1 Mode Resource" for more information on configuring Timer1. Note: Clocking Timer1 from the system clock (FOSC) should not be used in Compare mode. In order for Compare mode to recognize the trigger event on the CCPx pin, TImer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source.
23.2.3
SOFTWARE INTERRUPT MODE
The action on the pin is based on the value of the CCPxM<3:0> control bits of the CCPxCON register. At the same time, the interrupt flag CCPxIF bit is set. All Compare modes can generate an interrupt. Figure 23-2 shows a simplified diagram of the Compare operation.
When Generate Software Interrupt mode is chosen (CCPxM<3:0> = 1010), the CCPx module does not assert control of the CCPx pin (see the CCPxCON register).
23.2.4
SPECIAL EVENT TRIGGER
FIGURE 23-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
CCPxM<3:0> Mode Select Set CCPxIF Interrupt Flag (PIRx) 4 CCPRxH CCPRxL
When Special Event Trigger mode is chosen (CCPxM<3:0> = 1011), the CCPx module does the following: * Resets Timer1 * Starts an ADC conversion if ADC is enabled The CCPx module does not assert control of the CCPx pin in this mode. The Special Event Trigger output of the CCP occurs immediately upon a match between the TMR1H, TMR1L register pair and the CCPRxH, CCPRxL register pair. The TMR1H, TMR1L register pair is not reset until the next rising edge of the Timer1 clock. The Special Event Trigger output starts an A/D conversion (if the A/D module is enabled). This allows the CCPRxH, CCPRxL register pair to effectively provide a 16-bit programmable period register for Timer1.
CCPx Pin
Q
S R
Output Logic
Match
Comparator TMR1H TMR1L
TRIS Output Enable Special Event Trigger
TABLE 23-3: 23.2.1 CCP PIN CONFIGURATION
Device The user must configure the CCPx pin as an output by clearing the associated TRIS bit. Also, the CCPx pin function can be moved to alternative pins using the APFCON register. Refer to Section 12.1 "Alternate Pin Function" for more details. Note: Clearing the CCPxCON register will force the CCPx compare output latch to the default low level. This is not the PORT I/O data latch.
SPECIAL EVENT TRIGGER
CCPx/ECCPx ECCP1 CCP4
PIC16F/LF1826 PIC16F/LF1827
Refer to Section 15.2.5 "Special Event Trigger" for more information. Note 1: The Special Event Trigger from the CCP module does not set interrupt flag bit TMR1IF of the PIR1 register. 2: Removing the match condition by changing the contents of the CCPRxH and CCPRxL register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring.
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23.2.5 COMPARE DURING SLEEP 23.2.6 ALTERNATE PIN LOCATIONS
The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep. This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function registers, APFCON0 and APFCON1. To determine which pins can be moved and what their default locations are upon a Reset, see Section 12.1 "Alternate Pin Function" for more information.
TABLE 23-4:
Name APFCON0 CCPxCON CCPRxL CCPRxH CM1CON0 CM1CON1 CM2CON0 CM2CON1 INTCON PIE1 PIE2 PIE3
(2)
SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE
Bit 7 Bit 6 Bit 5 SS1SEL DCxB1 Bit 4 P2BSEL(2) DCxB0 Bit 3 CCP2SEL(2) CCPxM3 Bit 2 P1DSEL CCPxM2 Bit 1 P1CSEL CCPxM1 Bit 0 CCP1SEL CCPxM0 Register on Page 122 228 206* 206* -- -- -- -- IOCIE SSPIE BCL1IE TMR6IE SSPIF BCLIF TMR6IF T1OSCEN T1GGO/DONE C1SP -- C2SP -- TMR0IF CCP1IE -- -- CCP1IF -- -- T1SYNC T1GVAL C1HYS C1NCH1 C2HYS C2NCH1 INTF TMR2IE -- TMR4IE TMR2IF -- TMR4IF -- T1GSS1 C1SYNC C1NCH0 C2SYNC C2NCH0 IOCIF TMR1IE CCP2IE(2) -- TMR1IF CCP2IF(2) -- TMR1ON T1GSS0 172 173 172 173 91 92 93 94 96 97 98 187 188 179* 179* TRISA1 TRISB1 TRISA0 TRISB0 124 129
RXDTSEL SDO1SEL PxM1(1) PxM0(1)
Capture/Compare/PWM Register x Low Byte (LSB) Capture/Compare/PWM Register x High Byte (MSB) C1ON C1INTP C2ON C2INTP GIE TMR1GIE OSFIE -- TMR1GIF OSFIF -- TMR1GE C1OUT C1INTN C2OUT C2INTN PEIE ADIE C2IE -- ADIF C2IF -- T1GPOL C1OE C1PCH1 C2OE C2PCH1 TMR0IE RCIE C1IE CCP4IE RCIF C1IF CCP4IF T1CKPS1 T1GTM C1POL C1PCH0 C2POL C2PCH0 INTE TXIE EEIE CCP3IE TXIF EEIF CCP3IF T1CKPS0 T1GSPM
PIR1 PIR2 PIR3
(2)
T1CON T1GCON TMR1L TMR1H TRISA TRISB
TMR1CS1 TMR1CS0
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TRISA7 TRISB7 TRISA6 TRISB6 TRISA5 TRISB5 TRISA4 TRISB4 TRISA3 TRISB3 TRISA2 TRISB2
Legend: -- = Unimplemented locations, read as `0'. Shaded cells are not used by Compare mode. * Page provides register information. Note 1: Applies to ECCP modules only. 2: PIC16F/LF1827 only.
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23.3 PWM Overview
FIGURE 23-3:
Period Pulse Width
CCP PWM OUTPUT SIGNAL
Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in steps. A larger number of steps applied, which lengthens the pulse width, also supplies more power to the load. Lowering the number of steps applied, which shortens the pulse width, supplies less power. The PWM period is defined as the duration of one complete cycle or the total amount of on and off time combined. PWM resolution defines the maximum number of steps that can be present in a single PWM period. A higher resolution allows for more precise control of the pulse width time and in turn the power that is applied to the load. The term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, where 0% is fully off and 100% is fully on. A lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. Figure 23-3 shows a typical waveform of the PWM signal.
TMRx = PRx TMRx = CCPRxH:CCPxCON<5:4>
TMRx = 0
FIGURE 23-4:
SIMPLIFIED PWM BLOCK DIAGRAM
CCPxCON<5:4>
Duty Cycle Registers CCPRxL
CCPRxH(2) (Slave) CCPx Comparator
(1)
R S
Q
TMRx
TRIS Comparator
23.3.1
STANDARD PWM OPERATION
Note 1:
PRx
Clear Timer, toggle CCPx pin and latch duty cycle
The standard PWM function described in this section is available and identical for CCP modules ECCP1, ECCP2, CCP3 and CCP4. The standard PWM mode generates a Pulse-Width modulation (PWM) signal on the CCPx pin with up to 10 bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: * * * * PRx registers TxCON registers CCPRxL registers CCPxCON registers
2:
The 8-bit timer TMRx register is concatenated with the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. In PWM mode, CCPRxH is a read-only register.
Figure 23-4 shows a simplified block diagram of PWM operation. Note 1: The corresponding TRIS bit must be cleared to enable the PWM output on the CCPx pin. 2: Clearing the CCPxCON register will relinquish control of the CCPx pin.
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23.3.2 SETUP FOR PWM OPERATION
The following steps should be taken when configuring the CCP module for standard PWM operation: 1. 2. 3. Disable the CCPx pin output driver by setting the associated TRIS bit. Load the PRx register with the PWM period value. Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values. Load the CCPRxL register and the DCxBx bits of the CCPxCON register, with the PWM duty cycle value. Configure and start Timer2/4/6: * Select the Timer2/4/6 resource to be used for PWM generation by setting the CxTSEL<1:0> bits in the CCPTMRS register. * Clear the TMRxIF interrupt flag bit of the PIRx register. See Note below. * Configure the TxCKPS bits of the TxCON register with the Timer prescale value. * Enable the Timer by setting the TMRxON bit of the TxCON register. Enable PWM output pin: * Wait until the Timer overflows and the TMRxIF bit of the PIRx register is set. See Note below. * Enable the CCPx pin output driver by clearing the associated TRIS bit. Note: In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored. When TMRx is equal to PRx, the following three events occur on the next increment cycle: * TMRx is cleared * The CCPx pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) * The PWM duty cycle is latched from CCPRxL into CCPRxH. Note: The Timer postscaler (see Section 21.1 "Timer2/4/6 Operation") is not used in the determination of the PWM frequency.
4.
23.3.5
PWM DUTY CYCLE
5.
The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPRxL register and DCxB<1:0> bits of the CCPxCON register. The CCPRxL contains the eight MSbs and the DCxB<1:0> bits of the CCPxCON register contain the two LSbs. CCPRxL and DCxB<1:0> bits of the CCPxCON register can be written to at any time. The duty cycle value is not latched into CCPRxH until after the period completes (i.e., a match between PRx and TMRx registers occurs). While using the PWM, the CCPRxH register is read-only. Equation 12-2 is used to calculate the PWM pulse width. Equation 12-3 is used to calculate the PWM duty cycle ratio.
6.
EQUATION 23-2:
PULSE WIDTH
Pulse Width = CCPRxL:CCPxCON<5:4> TOSC (TMRx Prescale Value)
EQUATION 23-3:
DUTY CYCLE RATIO
23.3.3
TIMER2/4/6 TIMER RESOURCE
The PWM standard mode makes use of one of the 8-bit Timer2/4/6 timer resources to specify the PWM period. Configuring the CxTSEL<1:0> bits in the CCPTMRS register selects which Timer2/4/6 timer is used.
CCPRxL:CCPxCON<5:4> Duty Cycle Ratio = ---------------------------------------------------------------------4 PRx + 1 The CCPRxH register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. The 8-bit timer TMRx register is concatenated with either the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2/4/6 prescaler is set to 1:1. When the 10-bit time base matches the CCPRxH and 2-bit latch, then the CCPx pin is cleared (see Figure 23-4).
23.3.4
PWM PERIOD
The PWM period is specified by the PRx register of Timer2/4/6. The PWM period can be calculated using the formula of Equation 12-1.
EQUATION 23-1:
PWM PERIOD
(TMRx Prescale Value)
PWM Period = PRx + 1 4 TOSC
Note 1:
TOSC = 1/FOSC
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23.3.6 PWM RESOLUTION EQUATION 23-4: PWM RESOLUTION
The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PRx is 255. The resolution is a function of the PRx register value as shown by Equation 12-4. Note: log 4 PRx + 1 Resolution = ----------------------------------------- bits log 2
If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged.
TABLE 23-5:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 32 MHz)
1.95 kHz 16 0xFF 10 7.81 kHz 4 0xFF 10 31.25 kHz 1 0xFF 10 125 kHz 1 0x3F 8 250 kHz 1 0x1F 7 333.3 kHz 1 0x17 6.6
PWM Frequency Timer Prescale (1, 4, 16) PRx Value Maximum Resolution (bits)
TABLE 23-6:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
1.22 kHz 16 0xFF 10 4.88 kHz 4 0xFF 10 19.53 kHz 1 0xFF 10 78.12 kHz 1 0x3F 8 156.3 kHz 1 0x1F 7 208.3 kHz 1 0x17 6.6
PWM Frequency Timer Prescale (1, 4, 16) PRx Value Maximum Resolution (bits)
TABLE 23-7:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
1.22 kHz 16 0x65 8 4.90 kHz 4 0x65 8 19.61 kHz 1 0x65 8 76.92 kHz 1 0x19 6 153.85 kHz 1 0x0C 5 200.0 kHz 1 0x09 5
PWM Frequency Timer Prescale (1, 4, 16) PRx Value Maximum Resolution (bits)
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23.3.7 OPERATION IN SLEEP MODE 23.3.10 ALTERNATE PIN LOCATIONS
In Sleep mode, the TMRx register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, TMRx will continue from its previous state. This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function registers, APFCON0 and APFCON1. To determine which pins can be moved and what their default locations are upon a Reset, see Section 12.1 "Alternate Pin Function" for more information.
23.3.8
CHANGES IN SYSTEM CLOCK FREQUENCY
The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 5.0 "Oscillator Module (With Fail-Safe Clock Monitor)" for additional details.
23.3.9
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the CCP registers to their Reset states.
TABLE 23-8:
Name APFCON0 CCPxCON CCPxAS CCPTMRS INTCON PRx PSTRxCON PWMxCON TxCON TMRx TRISB
SUMMARY OF REGISTERS ASSOCIATED WITH PWM
Bit 7 Bit 6 SDO1SEL PxM0(1) CCPxAS2 C4TSEL0 PEIE -- PxDC6 Bit 5 SS1SEL DCxB1 CCPxAS1 C3TSEL1 TMR0IE -- PxDC5 Bit 4 Bit 3 Bit 2 P1DSEL CCPxM2 PSSxAC0 C2TSEL0 TMR0IF STRxC PxDC2 TMRxON TRISB2 Bit 1 P1CSEL CCPxM1 PSSxBD1 C1TSEL1 INTF STRxB PxDC1 TxCKPS1 TRISB1 Bit 0 CCP1SEL CCPxM0 PSSxBD0 C1TSEL0 IOCIF STRxA PxDC0 TxCKPS0 TRISB0 Register on Page 122 228 230 229 91 191* STRxSYNC PxDC4 STRxD PxDC3 232 231 193 191* TRISB5 TRISB4 TRISB3 129
RXDTSEL PxM1(1) CCPxASE C4TSEL1 GIE -- PxRSEN -- TRISB7
P2BSEL(2) CCP2SEL(2) DCxB0 CCPxAS0 C3TSEL0 INTE CCPxM3 PSSxAC1 C2TSEL1 IOCIE
Timerx Period Register
TxOUTPS3 TxOUTPS2 TxOUTPS1 TxOUTPS0 TRISB6
Timerx Module Register
Legend: -- = Unimplemented locations, read as `0'. Shaded cells are not used by the PWM. * Page provides register information. Note 1: Applies to ECCP modules only. 2: PIC16F/LF1827 only.
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23.4 PWM (Enhanced Mode)
The enhanced PWM function described in this section is available for CCP modules ECCP1, ECCP2 and ECCP3, with any differences between modules noted. The enhanced PWM mode generates a Pulse-Width Modulation (PWM) signal on up to four different output pins with up to 10 bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: * * * * PRx registers TxCON registers CCPRxL registers CCPxCON registers To select an Enhanced PWM Output mode, the PxM bits of the CCPxCON register must be configured appropriately. The PWM outputs are multiplexed with I/O pins and are designated PxA, PxB, PxC and PxD. The polarity of the PWM pins is configurable and is selected by setting the CCPxM bits in the CCPxCON register appropriately. Figure 23-5 shows an example of a simplified block diagram of the Enhanced PWM module. Figure 23-8 shows the pin assignments for various Enhanced PWM modes. Note 1: The corresponding TRIS bit must be cleared to enable the PWM output on the CCPx pin. 2: Clearing the CCPxCON register will relinquish control of the CCPx pin. 3: Any pin not used in the enhanced PWM mode is available for alternate pin functions, if applicable. 4: To prevent the generation of an incomplete waveform when the PWM is first enabled, the ECCP module waits until the start of a new PWM period before generating a PWM signal.
The ECCP modules have the following additional PWM registers which control Auto-shutdown, Auto-restart, Dead-band Delay and PWM Steering modes: * CCPxAS registers * PSTRxCON registers * PWMxCON registers The enhanced PWM module can generate the following five PWM Output modes: * * * * * Single PWM Half-Bridge PWM Full-Bridge PWM, Forward Mode Full-Bridge PWM, Reverse Mode Single PWM with PWM Steering Mode
FIGURE 23-5:
Duty Cycle Registers CCPRxL
EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE
DCxB<1:0> PxM<1:0> 2 CCPxM<3:0> 4
CCPx/PxA TRISx CCPRxH (Slave) Comparator R Q PxB Output Controller PxC TMRx (1) S PxD Clear Timer, toggle PWM pin and latch duty cycle PWMxCON TRISx TRISx TRISx
CCPx/PxA
PxB
PxC
Comparator
PxD
PRx
Note
1:
The 8-bit timer TMRx register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base.
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TABLE 23-9:
ECCP Mode Single Half-Bridge Full-Bridge, Forward Full-Bridge, Reverse Note 1:
EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES
PxM<1:0> 00 10 01 11 CCPx/PxA Yes(1) Yes Yes Yes PxB Yes(1) Yes Yes Yes PxC Yes(1) No Yes Yes PxD Yes(1) No Yes Yes
PWM Steering enables outputs in Single mode.
FIGURE 23-6:
PxM<1:0>
EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)
Signal 0 Pulse Width Period PRX+1
00
(Single Output)
PxA Modulated Delay PxA Modulated Delay
10
(Half-Bridge)
PxB Modulated PxA Active
01
(Full-Bridge, Forward)
PxB Inactive PxC Inactive PxD Modulated PxA Inactive
11
(Full-Bridge, Reverse)
PxB Modulated PxC Active PxD Inactive
Relationships: * Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) * Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value) * Delay = 4 * TOSC * (PWMxCON<6:0>)
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FIGURE 23-7:
PxM<1:0>
EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
Signal 0 Pulse Width Period PRx+1
00
(Single Output)
PxA Modulated PxA Modulated
10
(Half-Bridge)
Delay PxB Modulated PxA Active
Delay
01
(Full-Bridge, Forward)
PxB Inactive PxC Inactive PxD Modulated PxA Inactive
11
(Full-Bridge, Reverse)
PxB Modulated PxC Active PxD Inactive
Relationships: * Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) * Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value) * Delay = 4 * TOSC * (PWMxCON<6:0>)
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23.4.1 HALF-BRIDGE MODE
In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCPx/PxA pin, while the complementary PWM output signal is output on the PxB pin (see Figure 23-9). This mode can be used for Half-Bridge applications, as shown in Figure 23-9, or for Full-Bridge applications, where four power switches are being modulated with two PWM signals. In Half-Bridge mode, the programmable dead-band delay can be used to prevent shoot-through current in Half-Bridge power devices. The value of the PDC<6:0> bits of the PWMxCON register sets the number of instruction cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See Section 23.4.5 "Programmable Dead-Band Delay Mode" for more details of the dead-band delay operations. Since the PxA and PxB outputs are multiplexed with the PORT data latches, the associated TRIS bits must be cleared to configure PxA and PxB as outputs.
FIGURE 23-8:
EXAMPLE OF HALF-BRIDGE PWM OUTPUT
Period
Period Pulse Width PxA(2) td PxB(2)
(1)
td
(1)
(1)
td = Dead-Band Delay Note 1: 2: At this time, the TMRx register is equal to the PRx register. Output signals are shown as active-high.
FIGURE 23-9:
EXAMPLE OF HALF-BRIDGE APPLICATIONS
Standard Half-Bridge Circuit ("Push-Pull") FET Driver PxA
+ Load + -
FET Driver PxB
Half-Bridge Output Driving a Full-Bridge Circuit V+
FET Driver PxA Load
FET Driver
FET Driver PxB
FET Driver
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23.4.2 FULL-BRIDGE MODE
In Full-Bridge mode, all four pins are used as outputs. An example of Full-Bridge application is shown in Figure 23-10. In the Forward mode, pin CCPx/PxA is driven to its active state, pin PxD is modulated, while PxB and PxC will be driven to their inactive state as shown in Figure 23-11. In the Reverse mode, PxC is driven to its active state, pin PxB is modulated, while PxA and PxD will be driven to their inactive state as shown Figure 23-12. PxA, PxB, PxC and PxD outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the PxA, PxB, PxC and PxD pins as outputs.
FIGURE 23-10:
EXAMPLE OF FULL-BRIDGE APPLICATION
V+
FET Driver PxA
QA
QC
FET Driver
PxB FET Driver
Load FET Driver
PxC
QB
QD
VPxD
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FIGURE 23-11:
Forward Mode Period PxA
(2)
EXAMPLE OF FULL-BRIDGE PWM OUTPUT
Pulse Width PxB(2)
PxC(2)
PxD(2)
(1) (1)
Reverse Mode Period Pulse Width PxA(2) PxB(2) PxC(2)
PxD(2)
(1) (1)
Note 1: 2:
At this time, the TMRx register is equal to the PRx register. Output signal is shown as active-high.
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23.4.2.1 Direction Change in Full-Bridge Mode
In the Full-Bridge mode, the PxM1 bit in the CCPxCON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. A direction change is initiated in software by changing the PxM1 bit of the CCPxCON register. The following sequence occurs four Timer cycles prior to the end of the current PWM period: * The modulated outputs (PxB and PxD) are placed in their inactive state. * The associated unmodulated outputs (PxA and PxC) are switched to drive in the opposite direction. * PWM modulation resumes at the beginning of the next period. See Figure 23-13 for an illustration of this sequence. The Full-Bridge mode does not provide dead-band delay. As one output is modulated at a time, dead-band delay is generally not required. There is a situation where dead-band delay is required. This situation occurs when both of the following conditions are true: 1. 2. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. The turn off time of the power switch, including the power device and driver circuit, is greater than the turn on time.
Figure 23-13 shows an example of the PWM direction changing from forward to reverse, at a near 100% duty cycle. In this example, at time t1, the output PxA and PxD become inactive, while output PxC becomes active. Since the turn off time of the power devices is longer than the turn on time, a shoot-through current will flow through power devices QC and QD (see Figure 23-10) for the duration of `t'. The same phenomenon will occur to power devices QA and QB for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: 1. 2. Reduce PWM duty cycle for one PWM period before changing directions. Use switch drivers that can drive the switches off faster than they can drive them on.
Other options to prevent shoot-through current may exist.
FIGURE 23-12:
Signal
EXAMPLE OF PWM DIRECTION CHANGE
Period(1) Period
PxA (Active-High) PxB (Active-High) PxC (Active-High) PxD (Active-High) Pulse Width Note 1: 2: The direction bit PxM1 of the CCPxCON register is written any time during the PWM cycle. When changing directions, the PxA and PxC signals switch before the end of the current PWM cycle. The modulated PxB and PxD signals are inactive at this time. The length of this time is four Timer counts.
(2)
Pulse Width
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FIGURE 23-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
Forward Period t1 Reverse Period
PxA PxB PxC PxD PW
PW TON
External Switch C TOFF External Switch D Potential Shoot-Through Current T = TOFF - TON
Note 1: 2: 3:
All signals are shown as active-high. TON is the turn on delay of power switch QC and its driver. TOFF is the turn off delay of power switch QD and its driver.
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23.4.3 ENHANCED PWM AUTO-SHUTDOWN MODE
The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application. The auto-shutdown sources are selected using the CCPxAS<2:0> bits of the CCPxAS register. A shutdown event may be generated by: * A logic `0' on the INT pin * A logic `1' on a Comparator (Cx) output A shutdown condition is indicated by the CCPxASE (Auto-Shutdown Event Status) bit of the CCPxAS register. If the bit is a `0', the PWM pins are operating normally. If the bit is a `1', the PWM outputs are in the shutdown state. When a shutdown event occurs, two things happen: The CCPxASE bit is set to `1'. The CCPxASE will remain set until cleared in firmware or an auto-restart occurs (see Section 12.4.4 "Auto-Restart Mode"). The enabled PWM pins are asynchronously placed in their shutdown states. The PWM output pins are grouped into pairs [PxA/PxC] and [PxB/PxD]. The state of each pin pair is determined by the PSSxAC and PSSxBD bits of the CCPxAS register. Each pin pair may be placed into one of three states: * Drive logic `1' * Drive logic `0' * Tri-state (high-impedance) Note 1: The auto-shutdown condition is a level-based signal, not an edge-based signal. As long as the level is present, the auto-shutdown will persist. 2: Writing to the CCPxASE bit of the CCPxAS register is disabled while an auto-shutdown condition persists. 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart) the PWM signal will always restart at the beginning of the next PWM period. 4: Prior to an auto-shutdown event caused by a comparator output or INT pin event, a software shutdown can be triggered in firmware by setting the CCPxASE bit of the CCPxAS register to `1'. The Auto-Restart feature tracks the active status of a shutdown caused by a comparator output or INT pin event only. If it is enabled at this time, it will immediately clear this bit and restart the ECCP module at the beginning of the next PWM period.
FIGURE 23-14:
PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PXRSEN = 0)
Missing Pulse (Auto-Shutdown) Timer Overflow Timer Overflow PWM Period Timer Overflow Missing Pulse (CCPxASE not clear) Timer Overflow Timer Overflow
PWM Activity Start of PWM Period Shutdown Event CCPxASE bit Shutdown Event Occurs Shutdown Event Clears PWM Resumes CCPxASE Cleared by Firmware
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23.4.4 AUTO-RESTART MODE
The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PxRSEN bit in the PWMxCON register. If auto-restart is enabled, the CCPxASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the CCPxASE bit will be cleared via hardware and normal operation will resume.
FIGURE 23-15:
PWM AUTO-SHUTDOWN WITH AUTO-RESTART (PXRSEN = 1)
Missing Pulse (Auto-Shutdown) Timer Overflow Timer Overflow PWM Period Timer Overflow Missing Pulse (CCPxASE not clear) Timer Overflow Timer Overflow
PWM Activity Start of PWM Period Shutdown Event CCPxASE bit Shutdown Event Occurs Shutdown Event Clears PWM Resumes CCPxASE Cleared by Hardware
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23.4.5 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 23-16:
In Half-Bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off. During this brief interval, a very high current (shoot-through current) will flow through both power switches, shorting the bridge supply. To avoid this potentially destructive shoot-through current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. In Half-Bridge mode, a digitally programmable dead-band delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure 23-16 for illustration. The lower seven bits of the associated PWMxCON register (Figure 23-4) sets the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC).
EXAMPLE OF HALF-BRIDGE PWM OUTPUT
Period
Period Pulse Width PxA(2) td PxB(2)
(1)
td
(1)
(1)
td = Dead-Band Delay Note 1: 2: At this time, the TMRx register is equal to the PRx register. Output signals are shown as active-high.
FIGURE 23-17:
EXAMPLE OF HALF-BRIDGE APPLICATIONS
V+
Standard Half-Bridge Circuit ("Push-Pull") FET Driver PxA
+ V Load
FET Driver PxB
+ V -
V-
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23.4.6 PWM STEERING MODE
In Single Output mode, PWM steering allows any of the PWM pins to be the modulated signal. Additionally, the same PWM signal can be simultaneously available on multiple pins. Once the Single Output mode is selected (CCPxM<3:2> = 11 and PxM<1:0> = 00 of the CCPxCON register), the user firmware can bring out the same PWM signal to one, two, three or four output pins by setting the appropriate STRx bits of the PSTRxCON register, as shown in Register 23-5. Note: The associated TRIS bits must be set to output (`0') to enable the pin output driver in order to see the PWM signal on the pin.
While the PWM Steering mode is active, CCPxM<1:0> bits of the CCPxCON register select the PWM output polarity for the Px pins. The PWM auto-shutdown operation also applies to PWM Steering mode as described in Section 12.4.3 "Enhanced PWM Auto-shutdown mode". An auto-shutdown event will only affect pins that have PWM outputs enabled.
FIGURE 23-18:
STRxA PxA Signal CCPxM1 PORT Data STRxB CCPxM0 PORT Data STRxC CCPxM1 PORT Data STRxD CCPxM0 PORT Data
SIMPLIFIED STEERING BLOCK DIAGRAM
1 0 TRIS
PxA pin
1 0
PxB pin
TRIS
1 0 TRIS
PxC pin
1 0 TRIS
PxD pin
Note 1:
Port outputs are configured as shown when the CCPxCON register bits PxM<1:0> = 00 and CCPxM<3:2> = 11. Single PWM output requires setting at least one of the STRx bits.
2:
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23.4.6.1 Steering Synchronization
The STRxSYNC bit of the PSTRxCON register gives the user two selections of when the steering event will happen. When the STRxSYNC bit is `0', the steering event will happen at the end of the instruction that writes to the PSTRxCON register. In this case, the output signal at the Px pins may be an incomplete PWM waveform. This operation is useful when the user firmware needs to immediately remove a PWM signal from the pin. When the STRxSYNC bit is `1', the effective steering update will happen at the beginning of the next PWM period. In this case, steering on/off the PWM output will always produce a complete PWM waveform. Figures 12-19 and 12-20 illustrate the timing diagrams of the PWM steering depending on the STRxSYNC setting. configuration while the PWM pin output drivers are enable is not recommended since it may result in damage to the application circuits. The PxA, PxB, PxC and PxD output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pin output drivers at the same time as the Enhanced PWM modes may cause damage to the application circuit. The Enhanced PWM modes must be enabled in the proper Output mode and complete a full PWM cycle before enabling the PWM pin output drivers. The completion of a full PWM cycle is indicated by the TMRxIF bit of the PIRx register being set as the second PWM period begins. Note: When the microcontroller is released from Reset, all of the I/O pins are in the high-impedance state. The external circuits must keep the power switch devices in the Off state until the microcontroller drives the I/O pins with the proper signal levels or activates the PWM output(s).
23.4.7
START-UP CONSIDERATIONS 23.4.8
When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. The CCPxM<1:0> bits of the CCPxCON register allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (PxA/PxC and PxB/PxD). The PWM output polarities must be selected before the PWM pin output drivers are enabled. Changing the polarity
ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function registers, APFCON0 and APFCON1. To determine which pins can be moved and what their default locations are upon a Reset, see Section 12.1 "Alternate Pin Function" for more information.
FIGURE 23-19:
EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRxSYNC = 0)
PWM Period
PWM STRx
P1
PORT Data P1n = PWM
PORT Data
FIGURE 23-20:
EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRxSYNC = 1)
PWM
STRx
P1
PORT Data P1n = PWM
PORT Data
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TABLE 23-10: SUMMARY OF REGISTERS ASSOCIATED WITH ENHANCED PWM
Name APFCON0 CCPxCON CCPxAS CCPTMRS INTCON PIE1 PIE2 PIE3 PIR1 PIR2 PIR3 PR2 PR4 PR6 PSTRxCON PWMxCON T2CON T4CON T6CON TMR2 TMR4 TMR6 TRISA TRISB Bit 7 RXDTSEL CCPxASE C4TSEL<1:0> GIE TMR1GIE OSFIE -- TMR1GIF OSFIF -- PEIE ADIE C2IE -- ADIF C2IF -- Bit 6 SDO1SEL
(1)
Bit 5 SS1SEL CCPxAS<2:0>
Bit 4
Bit 3
Bit 2 P1DSEL
Bit 1 P1CSEL
Bit 0 CCP1SEL
Register on Page 122 228 230 229 91 92 93 94 96 97 98 191* 191* 191*
P2BSEL(2) CCP2SEL(2)
PxM<1:0>
DCxB<1:0> C3TSEL<1:0> TMR0IE RCIE C1IE CCP4IE RCIF C1IF CCP4IF INTE TXIE EEIE CCP3IE TXIF EEIF CCP3IF
CCPxM<3:0> PSSxAC<1:0> C2TSEL<1:0> IOCIE SSPIE BCLIE TMR6IE SSPIF BCLIF TMR6IF TMR0IF CCP1IE -- -- CCP1IF -- -- PSSxBD<1:0> C1TSEL<1:0> INTF TMR2IE -- TMR4IE TMR2IF -- TMR4IF IOCIF TMR1IE CCP2IE -- TMR1IF CCP2IF --
Timer2 Period Register Timer4 Module Period Register Timer6 Module Period Register -- PxRSEN -- -- -- -- -- STRxSYNC STRxD PxDC<6:0> T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 TMR2ON TMR4ON TMR6ON T2CKPS1 T4CKPS1 T6CKPS1 T2CKPS0 T4CKPS0 T6CKPS0 STRxC STRxB STRxA
232 231 193 193 193 191* 191* 191*
Holding Register for the 8-bit TMR2 Time Base Holding Register for the 8-bit TMR4 Time Base(1) Holding Register for the 8-bit TMR6 Time Base(1) TRISA7 TRISB7 TRISA6 TRISB6 TRISA5 TRISB5 TRISA4 TRISB4 TRISA3 TRISB3 TRISA2 TRISB2 TRISA1 TRISB1 TRISA0 TRISB0
124 129
Legend: -- = Unimplemented location, read as `0'. Shaded cells are not used by the PWM. * Page provides register information. Note 1: Applies to ECCP modules only. 2: PIC16F/LF1827 only.
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REGISTER 23-1:
R/W-00 bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6 W = Writable bit x = Bit is unknown `0' = Bit is cleared PxM<1:0>: Enhanced PWM Output Configuration bits(1) Capture mode: Unused Compare mode: Unused If CCPxM<3:2> = 00, 01, 10: xx = PxA assigned as Capture/Compare input; PxB, PxC, PxD assigned as port pins If CCPxM<3:2> = 11: 00 = Single output; PxA modulated; PxB, PxC, PxD assigned as port pins 01 = Full-Bridge output forward; PxD modulated; PxA active; PxB, PxC inactive 10 = Half-Bridge output; PxA, PxB modulated with dead-band control; PxC, PxD assigned as port pins 11 = Full-Bridge output reverse; PxB modulated; PxC active; PxA, PxD inactive bit 5-4 DCxB<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0 CCPxM<3:0>: ECCPx Mode Select bits 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = Capture/Compare/PWM off (resets ECCPx module) Reserved Compare mode: toggle output on match Reserved Capture mode: every falling edge Capture mode: every rising edge Capture mode: every 4th rising edge Capture mode: every 16th rising edge Compare mode: initialize ECCPx pin low; set output on compare match (set CCPxIF) Compare mode: initialize ECCPx pin high; clear output on compare match (set CCPxIF) Compare mode: generate software interrupt only; ECCPx pin reverts to I/O state Compare mode: Special Event Trigger (ECCPx resets TMR1 or TMR3, sets CCPxIF bit, ECCP2 trigger also starts A/D conversion if A/D module is enabled)(1) U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Reset PxM<1:0>(1)
CCPxCON: CCPx CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 bit 0 DCxB<1:0> CCPxM<3:0>
R/W-0/0
CCP Modules only: 11xx = PWM mode ECCP Modules only: 1100 = PWM mode: PxA, PxC active-high; PxB, PxD active-high 1101 = PWM mode: PxA, PxC active-high; PxB, PxD active-low 1110 = PWM mode: PxA, PxC active-low; PxB, PxD active-high 1111 = PWM mode: PxA, PxC active-low; PxB, PxD active-low Note 1: These bits are not implemented on CCP<4:3>.
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REGISTER 23-2:
R/W-0/0 bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6 W = Writable bit x = Bit is unknown `0' = Bit is cleared C4TSEL<1:0>: CCP4 Timer Selection 00 = CCP4 is based off Timer 2 in PWM Mode 01 = CCP4 is based off Timer 4 in PWM Mode 10 = CCP4 is based off Timer 6 in PWM Mode 11 = Reserved C3TSEL<1:0>: CCP3 Timer Selection 00 = CCP3 is based off Timer 2 in PWM Mode 01 = CCP3 is based off Timer 4 in PWM Mode 10 = CCP3 is based off Timer 6 in PWM Mode 11 = Reserved C2TSEL<1:0>: CCP2 Timer Selection 00 = CCP2 is based off Timer 2 in PWM Mode 01 = CCP2 is based off Timer 4 in PWM Mode 10 = CCP2 is based off Timer 6 in PWM Mode 11 = Reserved C1TSEL<1:0>: CCP1 Timer Selection 00 = CCP1 is based off Timer 2 in PWM Mode 01 = CCP1 is based off Timer 4 in PWM Mode 10 = CCP1 is based off Timer 6 in PWM Mode 11 = Reserved U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets C4TSEL<1:0>
CCPTMRS: PWM TIMER SELECTION CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 bit 0 C3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0>
R/W-0/0
bit 5-4
bit 3-2
bit 1-0
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REGISTER 23-3:
R/W-0/0 CCPxASE bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared CCPxASE: CCPx Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; CCPx outputs are in shutdown state 0 = CCPx outputs are operating CCxPAS<2:0>: CCPx Auto-Shutdown Source Select bits 000 = Auto-shutdown is disabled 001 = Comparator C1 output high(1) 010 = Comparator C2 output high(1) 011 = Either Comparator C1 or C2 high(1) 100 = VIL on INT pin 101 = VIL on INT pin or Comparator C1 high(1) 110 = VIL on INT pin or Comparator C2 high(1) 111 = VIL on INT pin or Comparator C1 or Comparator C2 high(1) PSSxAC<1:0>: Pins PxA and PxC Shutdown State Control bits 00 = Drive pins PxA and PxC to `0' 01 = Drive pins PxA and PxC to `1' 1x = Pins PxA and PxC tri-state PSSxBD<1:0>: Pins PxB and PxD Shutdown State Control bits 00 = Drive pins PxB and PxD to `0' 01 = Drive pins PxB and PxD to `1' 1x = Pins PxB and PxD tri-state If CxSYNC is enabled, the shutdown will be delayed by Timer1. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
CCPxAS: CCPx AUTO-SHUTDOWN CONTROL REGISTER
R/W-0/0 CCPxAS<2:0> R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 bit 0 PSSxAC<1:0> PSSxBD<1:0>
R/W-0/0
bit 6-4
bit 3-2
bit 1-0
Note 1:
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REGISTER 23-4:
R/W-0/0 PxRSEN bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared PxRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the CCPxASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, CCPxASE must be cleared in software to restart the PWM PxDC<6:0>: PWM Delay Count bits PxDCx = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active Bit resets to `0' with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe mode is enabled. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
PWMxCON: ENHANCED PWM CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 PxDC<6:0> bit 0 R/W-0/0 R/W-0/0 R/W-0/0
R/W-0/0
bit 6-0
Note 1:
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REGISTER 23-5:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-5 bit 4 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0' STRxSYNC: Steering Sync bit 1 = Output steering update occurs on next PWM period 0 = Output steering update occurs at the beginning of the instruction cycle boundary STRxD: Steering Enable bit D 1 = PxD pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxD pin is assigned to port pin STRxC: Steering Enable bit C 1 = PxC pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxC pin is assigned to port pin STRxB: Steering Enable bit B 1 = PxB pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxB pin is assigned to port pin STRxA: Steering Enable bit A 1 = PxA pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxA pin is assigned to port pin The PWM Steering mode is available only when the CCPxCON register bits CCPxM<3:2> = 11 and PxM<1:0> = 00. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
PSTRxCON: PWM STEERING CONTROL REGISTER(1)
U-0 -- U-0 -- R/W-0/0 STRxSYNC R/W-0/0 STRxD R/W-0/0 STRxC R/W-0/0 STRxB R/W-1/1 STRxA bit 0
bit 3
bit 2
bit 1
bit 0
Note 1:
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24.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP1 AND MSSP2) MODULE
Master SSPx (MSSPx) Module Overview
24.1
The Master Synchronous Serial Port (MSSPx) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSPx module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2CTM) The SPI interface supports the following modes and features: * * * * * Master mode Slave mode Clock Parity Slave Select Synchronization (Slave mode only) Daisy chain connection of slave devices
Figure 24-1 is a block diagram of the SPI interface module.
FIGURE 24-1:
MSSPX BLOCK DIAGRAM (SPI MODE)
Data Bus Read SSPxBUF Reg Write
SDIx SSPxSR Reg SDOx bit 0 Shift Clock
SSx
SSx Control Enable Edge Select SSPxM<3:0> 4
2 (CKP, CKE) Clock Select
SCKx Edge Select
( TMR22Output )
Prescaler TOSC 4, 16, 64 Baud Rate Generator (SSPxADD)
TRIS bit
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The I2C interface supports the following modes and features: * * * * * * * * * * * * * Master mode Slave mode Byte NACKing (Slave mode) Limited Multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDAx hold times The PIC16F1827 has two MSSP modules, MSSP1 and MSSP2, each module operating independently from the other. Note 1: In devices with more than one MSSP module, it is very important to pay close attention to SSPxCONx register names. SSP1CON1 and SSP1CON2 registers control different operational aspects of the same module, while SSP1CON1 and SSP2CON1 control the same features for two different modules. 2: Throughout this section, generic references to an MSSP module in any of its operating modes may be interpreted as being equally applicable to MSSP1 or MSSP2. Register names, module I/O signals, and bit names may use the generic designator `x' to indicate the use of a numeral to distinguish a particular module when required.
Figure 24-2 is a block diagram of the I2C interface module in Master mode. Figure 24-3 is a diagram of the I2C interface module in Slave mode.
FIGURE 24-2:
MSSPX BLOCK DIAGRAM (I2CTM MASTER MODE)
Internal data bus Read SSPxBUF Write Baud rate generator (SSPxADD) Shift Clock SSPxSR Clock Cntl MSb Receive Enable (RCEN) LSb Clock arbitrate/BCOL detect (Hold off clock source)
[SSPxM 3:0]
SDAx SDAx in
Start bit, Stop bit, Acknowledge Generate (SSPxCON2)
SCLx
SCLx in Bus Collision
Start bit detect, Stop bit detect Write collision detect Clock arbitration State counter for end of XMIT/RCV Address Match detect
Set/Reset: S, P, SSPxSTAT, WCOL, SSPxOV Reset SEN, PEN (SSPxCON2) Set SSPxIF, BCLxIF
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FIGURE 24-3: MSSPX BLOCK DIAGRAM (I2CTM SLAVE MODE)
Internal Data Bus Read SSPxBUF Reg Shift Clock SSPxSR Reg SDAx MSb LSb Write
SCLx
SSPxMSK Reg Match Detect SSPxADD Reg Start and Stop bit Detect Set, Reset S, P bits (SSPxSTAT Reg) Addr Match
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24.2 SPI Mode Overview
The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a chip select known as Slave Select. The SPI bus specifies four signal connections: * * * * Serial Clock (SCKx) Serial Data Out (SDOx) Serial Data In (SDIx) Slave Select (SSx) it's SDOx pin) and the slave device is reading this bit and saving it as the LSb of its shift register, that the slave device is also sending out the MSb from its shift register (on its SDOx pin) and the master device is reading this bit and saving it as the LSb of its shift register. After 8 bits have been shifted out, the master and slave have exchanged register values. If there is more data to exchange, the shift registers are loaded with new data and the process repeats itself. Whether the data is meaningful or not (dummy data), depends on the application software. This leads to three scenarios for data transmission: * Master sends useful data and slave sends dummy data. * Master sends useful data and slave sends useful data. * Master sends dummy data and slave sends useful data. Transmissions may involve any number of clock cycles. When there is no more data to be transmitted, the master stops sending the clock signal and it deselects the slave. Every slave device connected to the bus that has not been selected through its slave select line must disregard the clock and transmission signals and must not transmit out any data of its own.
Figure 24-1 shows the block diagram of the MSSPx module when operating in SPI Mode. The SPI bus operates with a single master device and one or more slave devices. When multiple slave devices are used, an independent Slave Select connection is required from the master device to each slave device. Figure 24-4 shows a typical connection between a master device and multiple slave devices. The master selects only one slave at a time. Most slave devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected. Transmissions involve two shift registers, eight bits in size, one in the master and one in the slave. With either the master or the slave device, data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register. Figure 24-5 shows a typical connection between two processors configured as master and slave devices. Data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock. The master device transmits information out on its SDOx output pin which is connected to, and received by, the slave's SDIx input pin. The slave device transmits information out on its SDOx output pin, which is connected to, and received by, the master's SDIx input pin. To begin communication, the master device first sends out the clock signal. Both the master and the slave devices should be configured for the same clock polarity. The master device starts a transmission by sending out the MSb from its shift register. The slave device reads this bit from that same line and saves it into the LSb position of its shift register. During each SPI clock cycle, a full duplex data transmission occurs. This means that while the master device is sending out the MSb from its shift register (on
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FIGURE 24-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION
SCKx SDOx SDIx General I/O General I/O General I/O SCKx SDIx SDOx SSx SCKx SDIx SDOx SSx SCKx SDIx SDOx SSx SPI Slave #3 SPI Slave #2 SPI Slave #1
SPI Master
24.2.1
SPI MODE REGISTERS
The MSSPx module has five registers for SPI mode operation. These are: * * * * * * MSSPx STATUS register (SSPxSTAT) MSSPx Control Register 1 (SSPxCON1) MSSPx Control Register 3 (SSPxCON3) MSSPx Data Buffer register (SSPxBUF) MSSPx Address register (SSPxADD) MSSPx Shift register (SSPxSR) (Not directly accessible)
SSPxCON1 and SSPxSTAT are the control and STATUS registers in SPI mode operation. The SSPxCON1 register is readable and writable. The lower 6 bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. In one SPI master mode, SSPxADD can be loaded with a value used in the Baud Rate Generator. More information on the Baud Rate Generator is available in Section 24.7 "Baud Rate Generator". SSPxSR is the shift register used for shifting data in and out. SSPxBUF provides indirect access to the SSPxSR register. SSPxBUF is the buffer register to which data bytes are written, and from which data bytes are read. In receive operations, SSPxSR and SSPxBUF together create a buffered receiver. When SSPxSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set. During transmission, the SSPxBUF is not buffered. A write to SSPxBUF will write to both SSPxBUF and SSPxSR.
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24.2.2 SPI MODE OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). These control bits allow the following to be specified: Master mode (SCKx is the clock output) Slave mode (SCKx is the clock input) Clock Polarity (Idle state of SCKx) Data Input Sample Phase (middle or end of data output time) * Clock Edge (output data on rising/falling edge of SCKx) * Clock Rate (Master mode only) * Slave Select mode (Slave mode only) To enable the serial port, SSPx Enable bit, SSPxEN of the SSPxCON1 register, must be set. To reset or reconfigure SPI mode, clear the SSPxEN bit, re-initialize the SSPxCONx registers and then set the SSPxEN bit. This configures the SDIx, SDOx, SCKx and SSx pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows: * SDIx must have corresponding TRIS bit set * SDOx must have corresponding TRIS bit cleared * SCKx (Master mode) must have corresponding TRIS bit cleared * SCKx (Slave mode) must have corresponding TRIS bit set * SSx must have corresponding TRIS bit set * * * * Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. The MSSPx consists of a transmit/receive shift register (SSPxSR) and a buffer register (SSPxBUF). The SSPxSR shifts the data in and out of the device, MSb first. The SSPxBUF holds the data that was written to the SSPxSR until the received data is ready. Once the 8 bits of data have been received, that byte is moved to the SSPxBUF register. Then, the Buffer Full Detect bit, BF of the SSPxSTAT register, and the interrupt flag bit, SSPxIF, are set. This double-buffering of the received data (SSPxBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPxBUF register during transmission/reception of data will be ignored and the write collision detect bit WCOL of the SSPxCON1 register, will be set. User software must clear the WCOL bit to allow the following write(s) to the SSPxBUF register to complete successfully. When the application software is expecting to receive valid data, the SSPxBUF should be read before the next byte of data to transfer is written to the SSPxBUF. The Buffer Full bit, BF of the SSPxSTAT register, indicates when SSPxBUF has been loaded with the received data (transmission is complete). When the SSPxBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSPx interrupt is used to determine when the transmission/reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur.
FIGURE 24-5:
SPI MASTER/SLAVE CONNECTION
SPI Slave SSPxM<3:0> = 010x SDIx Serial Input Buffer (SSPxBUF)
SPI Master SSPxM<3:0> = 00xx = 1010 SDOx Serial Input Buffer (BUF)
Shift Register (SSPxSR) MSb LSb
SDIx
SDOx MSb SCKx SSx
Shift Register (SSPxSR) LSb
SCKx General I/O Processor 1
Serial Clock Slave Select (optional)
Processor 2
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24.2.3 SPI MASTER MODE
The master can initiate the data transfer at any time because it controls the SCKx line. The master determines when the slave (Processor 2, Figure 24-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDOx output could be disabled (programmed as an input). The SSPxSR register will continue to shift in the signal present on the SDIx pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPxBUF register as if a normal received byte (interrupts and Status bits appropriately set). The clock polarity is selected by appropriately programming the CKP bit of the SSPxCON1 register and the CKE bit of the SSPxSTAT register. This then, would give waveforms for SPI communication as shown in Figure 24-6, Figure 24-8 and Figure 24-9, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: * * * * * FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 Fosc/(4 * (SSPxADD + 1))
Figure 24-6 shows the waveforms for Master mode. When the CKE bit is set, the SDOx data is valid before there is a clock edge on SCKx. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received data is shown.
FIGURE 24-6:
Write to SSPxBUF SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) SDOx (CKE = 0) SDOx (CKE = 1) SDIx (SMP = 0) Input Sample (SMP = 0) SDIx (SMP = 1) Input Sample (SMP = 1) SSPxIF SSPxSR to SSPxBUF
SPI MODE WAVEFORM (MASTER MODE)
4 Clock Modes
bit 7 bit 7
bit 6 bit 6
bit 5 bit 5
bit 4 bit 4
bit 3 bit 3
bit 2 bit 2
bit 1 bit 1
bit 0 bit 0
bit 7
bit 0
bit 7
bit 0
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24.2.4 SPI SLAVE MODE
24.2.5
In Slave mode, the data is transmitted and received as external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCKx pin. The Idle state is determined by the CKP bit of the SSPxCON1 register. While in Slave mode, the external clock is supplied by the external clock source on the SCKx pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. The shift register is clocked from the SCKx pin input and when a byte is received, the device will generate an interrupt. If enabled, the device will wake-up from Sleep. 24.2.4.1 Daisy-Chain Configuration
SLAVE SELECT SYNCHRONIZATION
The Slave Select can also be used to synchronize communication. The Slave Select line is held high until the master device is ready to communicate. When the Slave Select line is pulled low, the slave knows that a new transmission is starting. If the slave fails to receive the communication properly, it will be reset at the end of the transmission, when the Slave Select line returns to a high state. The slave is then ready to receive a new transmission when the Slave Select line is pulled low again. If the Slave Select line is not used, there is a risk that the slave will eventually become out of sync with the master. If the slave misses a bit, it will always be one bit off in future transmissions. Use of the Slave Select line allows the slave and master to align themselves at the beginning of each transmission. The SSx pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SSx pin control enabled (SSPxCON1<3:0> = 0100). When the SSx pin is low, transmission and reception are enabled and the SDOx pin is driven. When the SSx pin goes high, the SDOx pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Slave mode with SSx pin control enabled (SSPxCON1<3:0> = 0100), the SPI module will reset if the SSx pin is set to VDD. 2: When the SPI is used in Slave mode with CKE set; the user must enable SSx pin control. 3: While operated in SPI Slave mode the SMP bit of the SSPxSTAT register must remain clear. When the SPI module resets, the bit counter is forced to `0'. This can be done by either forcing the SSx pin to a high level or clearing the SSPxEN bit.
The SPI bus can sometimes be connected in a daisy-chain configuration. The first slave output is connected to the second slave input, the second slave output is connected to the third slave input, and so on. The final slave output is connected to the master input. Each slave sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. The whole chain acts as one large communication shift register. The daisy-chain feature only requires a single Slave Select line from the master device. Figure 24-7 shows the block diagram of a typical Daisy-Chain connection when operating in SPI Mode. In a daisy-chain configuration, only the most recent byte on the bus is required by the slave. Setting the BOEN bit of the SSPxCON3 register will enable writes to the SSPxBUF register, even if the previous byte has not been read. This allows the software to ignore data that may not apply to it.
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FIGURE 24-7: SPI DAISY-CHAIN CONNECTION
SCK SDOx SDIx General I/O SCK SDIx SDOx SSx SCK SDIx SDOx SSx SCK SDIx SDOx SSx SPI Slave #3 SPI Slave #2 SPI Slave #1
SPI Master
FIGURE 24-8:
SSx SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SSPxBUF to SSPxSR
SLAVE SELECT SYNCHRONOUS WAVEFORM
Shift register SSPxSR and bit count are reset
SDOx
bit 7
bit 6
bit 7
bit 6
bit 0
SDIx bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF bit 7
bit 0
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FIGURE 24-9:
SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF Valid SDOx SDIx bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
FIGURE 24-10:
SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF Valid SDOx SDIx
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7 Input Sample
bit 0
SSPxIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active
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24.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, module clocks may be operating at a different speed than when in full power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSPx clock is much faster than the system clock. In Slave mode, when MSSPx interrupts are enabled, after the master completes sending data, an MSSPx interrupt will wake the controller from Sleep. If an exit from Sleep mode is not desired, MSSPx interrupts should be disabled. In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all 8 bits have been received, the MSSPx interrupt flag bit will be set and if enabled, will wake the device.
TABLE 24-1:
Name APFCON0 ANSELA ANSELB INTCON PIE1 PIR1 SSPxBUF SSPxCON1 SSPxCON3 SSPxSTAT TRISA TRISB Legend: * Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
Bit 7 Bit 6 SDO1SEL -- ANSB6 PEIE ADIE ADIF Bit 5 SS1SEL -- ANSB5 TMR0IE RCIE RCIF Bit 4 Bit 3 Bit 2 P1DSEL ANSA2 ANSB2 TMR0IF CCP1IE CCP1IF Bit 1 P1CSEL ANSA1 ANSB1 INTF TMR2IE TMR2IF Bit 0 CCP1SEL ANSA0 -- IOCIF TMR1IE TMR1IF Register on Page 122 125 130 91 92 96 237* SSPxM2 SBCDE R/W TRISA2 TRISB2 SSPxM1 AHEN UA TRISA1 TRISB1 SSPxM0 DHEN BF TRISA0 TRISB0 283 285 282 124 129
RXDTSEL -- ANSB7 GIE TMR1GIE TMR1GIF
P2BSEL(1) CCP2SEL(1) ANSA4 ANSB4 INTE TXIE TXIF ANSA3 ANSB3 IOCIE SSP1IE SSP1IF
Synchronous Serial Port Receive Buffer/Transmit Register WCOL ACKTIM SMP TRISA7 TRISB7 SSPxOV PCIE CKE TRISA6 TRISB6 SSPxEN SCIE D/A TRISA5 TRISB5 CKP BOEN P TRISA4 TRISB4 SSPxM3 SDAHT S TRISA3 TRISB3
-- = Unimplemented location, read as `0'. Shaded cells are not used by the MSSPx in SPI mode. Page provides register information. PIC16F/LF1827 only.
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24.3
I2C MODE OVERVIEW FIGURE 24-11:
The Inter-Integrated Circuit Bus (IC) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A Slave device is controlled through addressing. The I2C bus specifies two signal connections: * Serial Clock (SCLx) * Serial Data (SDAx) Figure 24-11 shows the block diagram of the MSSPx module when operating in I2C Mode. Both the SCLx and SDAx connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. Pulling the line to ground is considered a logical zero and letting the line float is considered a logical one. Figure 24-11 shows a typical connection between two processors configured as master and slave devices. The I2C bus can operate with one or more master devices and one or more slave devices. There are four potential modes of operation for a given device: * Master Transmit mode (master is transmitting data to a slave) * Master Receive mode (master is receiving data from a slave) * Slave Transmit mode (slave is transmitting data to a master) * Slave Receive mode (slave is receiving data from the master) To begin communication, a master device starts out in Master Transmit mode. The master device sends out a Start bit followed by the address byte of the slave it intends to communicate with. This is followed by a single Read/Write bit, which determines whether the master intends to transmit to or receive data from the slave device. If the requested slave exists on the bus, it will respond with an Acknowledge bit, otherwise known as an ACK. The master then continues in either Transmit mode or Receive mode and the slave continues in the complement, either in Receive mode or Transmit mode, respectively. A Start bit is indicated by a high-to-low transition of the SDAx line while the SCLx line is held high. Address and data bytes are sent out, Most Significant bit (MSb) first. The Read/Write bit is sent out as a logical one when the master intends to read data from the slave, and is sent out as a logical zero when it intends to write data to the slave. Master SDAx
I2C MASTER/ SLAVE CONNECTION
VDD
SCLx VDD
SCLx Slave SDAx
The Acknowledge bit (ACK) is an active-low signal, which holds the SDAx line low to indicate to the transmitter that the slave device has received the transmitted data and is ready to receive more. The transition of a data bit is always performed while the SCLx line is held low. Transitions that occur while the SCLx line is held high are used to indicate Start and Stop bits. If the master intends to write to the slave, then it repeatedly sends out a byte of data, with the slave responding after each byte with an ACK bit. In this example, the master device is in Master Transmit mode and the slave is in Slave Receive mode. If the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and responds after each byte with an ACK bit. In this example, the master device is in Master Receive mode and the slave is Slave Transmit mode. On the last byte of data communicated, the master device may end the transmission by sending a Stop bit. If the master device is in Receive mode, it sends the Stop bit in place of the last ACK bit. A Stop bit is indicated by a low-to-high transition of the SDAx line while the SCLx line is held high. In some cases, the master may want to maintain control of the bus and re-initiate another transmission. If so, the master device may send another Start bit in place of the Stop bit or last ACK bit when it is in receive mode. The I2C bus specifies three message protocols; * Single message where a master writes data to a slave. * Single message where a master reads data from a slave. * Combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes and reads, to one or more slaves.
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When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCLx line, is called clock stretching. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on the SDAx line, it is called arbitration. Arbitration ensures that there is only one master device communicating at any single time.
24.3.2
ARBITRATION
Each master device must monitor the bus for Start and Stop bits. If the device detects that the bus is busy, it cannot begin a new message until the bus returns to an Idle state. However, two master devices may try to initiate a transmission on or about the same time. When this occurs, the process of arbitration begins. Each transmitter checks the level of the SDAx data line and compares it to the level that it expects to find. The first transmitter to observe that the two levels don't match, loses arbitration, and must stop transmitting on the SDAx line. For example, if one transmitter holds the SDAx line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the SDAx line will be low. The first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating. The first transmitter to notice this difference is the one that loses arbitration and must stop driving the SDAx line. If this transmitter is also a master device, it also must stop driving the SCLx line. It then can monitor the lines for a Stop condition before trying to reissue its transmission. In the meantime, the other device that has not noticed any difference between the expected and actual levels on the SDAx line continues with it's original transmission. It can do so without any complications, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. Slave Transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. If two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitration. When two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. Arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support.
24.3.1
CLOCK STRETCHING
When a slave device has not completed processing data, it can delay the transfer of more data through the process of Clock Stretching. An addressed slave device may hold the SCLx clock line low after receiving or sending a bit, indicating that it is not yet ready to continue. The master that is communicating with the slave will attempt to raise the SCLx line in order to transfer the next bit, but will detect that the clock line has not yet been released. Because the SCLx connection is open-drain, the slave has the ability to hold that line low until it is ready to continue communicating. Clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data.
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24.4
I2C MODE OPERATION TABLE 24-2:
TERM Transmitter
I2C BUS TERMS
Description
All MSSPx I2C communication is byte oriented and shifted out MSb first. Six SFR registers and 2 interrupt flags interface the module with the PIC(R) microcontroller and user software. Two pins, SDAx and SCLx, are exercised by the module to communicate with other external I2C devices. 24.4.1 BYTE FORMAT
All communication in I2C is done in 9-bit segments. A byte is sent from a Master to a Slave or vice-versa, followed by an Acknowledge bit sent back. After the 8th falling edge of the SCLx line, the device outputting data on the SDAx changes that pin to an input and reads in an acknowledge value on the next clock pulse. The clock signal, SCLx, is provided by the master. Data is valid to change while the SCLx signal is low, and sampled on the rising edge of the clock. Changes on the SDAx line while the SCLx line is high define special conditions on the bus, explained below. 24.4.2 DEFINITION OF I2C TERMINOLOGY
There is language and terminology in the description of I2C communication that have definitions specific to I2C. That word usage is defined below and may be used in the rest of this document without explanation. This table was adapted from the Phillips I2C specification. 24.4.3 SDAX AND SCLX PINS
Selection of any I2C mode with the SSPxEN bit set, forces the SCLx and SDAx pins to be open-drain. These pins should be set by the user to inputs by setting the appropriate TRIS bits. Note: Data is tied to output zero when an I2C mode is enabled. 24.4.4 SDAX HOLD TIME
The hold time of the SDAx pin is selected by the SDAHT bit of the SSPxCON3 register. Hold time is the time SDAx is held valid after the falling edge of SCLx. Setting the SDAHT bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance.
The device which shifts data out onto the bus. Receiver The device which shifts data in from the bus. Master The device that initiates a transfer, generates clock signals and terminates a transfer. Slave The device addressed by the master. Multi-master A bus with more than one device that can initiate data transfers. Arbitration Procedure to ensure that only one master at a time controls the bus. Winning arbitration ensures that the message is not corrupted. Synchronization Procedure to synchronize the clocks of two or more devices on the bus. Idle No master is controlling the bus, and both SDAx and SCLx lines are high. Active Any time one or more master devices are controlling the bus. Slave device that has received a Addressed Slave matching address and is actively being clocked by a master. Matching Address byte that is clocked into a Address slave that matches the value stored in SSPxADD. Write Request Slave receives a matching address with R/W bit clear, and is ready to clock in data. Read Request Master sends an address byte with the R/W bit set, indicating that it wishes to clock data out of the Slave. This data is the next and all following bytes until a Restart or Stop. Clock Stretching When a device on the bus hold SCLx low to stall communication. Bus Collision Any time the SDAx line is sampled low by the module while it is outputting and expected high state.
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24.4.5 START CONDITION 24.4.7 RESTART CONDITION The I2C specification defines a Start condition as a transition of SDAx from a high to a low state while SCLx line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state. Figure 24-10 shows wave forms for Start and Stop conditions. A bus collision can occur on a Start condition if the module samples the SDAx line low before asserting it low. This does not conform to the I2C Specification that states no bus collision can occur on a Start. 24.4.6 STOP CONDITION A Restart is valid any time that a Stop would be valid. A master can issue a Restart if it wishes to hold the bus after terminating the current transfer. A Restart has the same effect on the slave that a Start would, resetting all slave logic and preparing it to clock in an address. The master may want to address the same or another slave. In 10-bit Addressing Slave mode a Restart is required for the master to clock data out of the addressed slave. Once a slave has been fully addressed, matching both high and low address bytes, the master can issue a Restart and the high address byte with the R/W bit set. The slave logic will then hold the clock and prepare to clock out data. After a full match with R/W clear in 10-bit mode, a prior match flag is set and maintained. Until a Stop condition, a high address with R/W clear, or high address match fails. 24.4.8 START/STOP CONDITION INTERRUPT MASKING
A Stop condition is a transition of the SDAx line from low-to-high state while the SCLx line is high. Note: At least one SCLx low time must appear before a Stop is valid, therefore, if the SDAx line goes low then high again while the SCLx line stays high, only the Start condition is detected.
The SCIE and PCIE bits of the SSPxCON3 register can enable the generation of an interrupt in Slave modes that do not typically support this function. Slave modes where interrupt on Start and Stop detect are already enabled, these bits will have no effect.
FIGURE 24-12:
I2C START AND STOP CONDITIONS
SDAx
SCLx S Change of Start Condition Data Allowed Change of Data Allowed Stop Condition P
FIGURE 24-13:
I2C RESTART CONDITION
Sr Change of Data Allowed Restart Condition Change of Data Allowed
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24.4.9 ACKNOWLEDGE SEQUENCE
24.5
I2C SLAVE MODE OPERATION
The 9th SCLx pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDAx line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDAx line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more. The result of an ACK is placed in the ACKSTAT bit of the SSPxCON2 register. Slave software, when the AHEN and DHEN bits are set, allow the user to set the ACK value sent back to the transmitter. The ACKDT bit of the SSPxCON2 register is set/cleared to determine the response. Slave hardware will generate an ACK response if the AHEN and DHEN bits of the SSPxCON3 register are clear. There are certain conditions where an ACK will not be sent by the slave. If the BF bit of the SSPxSTAT register or the SSPxOV bit of the SSPxCON1 register are set when a byte is received. When the module is addressed, after the 8th falling edge of SCLx on the bus, the ACKTIM bit of the SSPxCON3 register is set. The ACKTIM bit indicates the acknowledge time of the active bus. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is enabled.
The MSSPx Slave mode operates in one of four modes selected in the SSPxM bits of SSPxCON1 register. The modes can be divided into 7-bit and 10-bit Addressing mode. 10-bit Addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses. Modes with Start and Stop bit interrupts operated the same as the other modes with SSPxIF additionally getting set upon detection of a Start, Restart, or Stop condition. 24.5.1 SLAVE MODE ADDRESSES
The SSPxADD register (Register 24-6) contains the Slave mode address. The first byte received after a Start or Restart condition is compared against the value stored in this register. If the byte matches, the value is loaded into the SSPxBUF register and an interrupt is generated. If the value does not match, the module goes idle and no indication is given to the software that anything happened. The SSPx Mask register (Register 24-5) affects the address matching process. See Section 24.5.9 "SSPx Mask Register" for more information. 24.5.1.1 I2C Slave 7-bit Addressing Mode
In 7-bit Addressing mode, the LSb of the received data byte is ignored when determining if there is an address match. 24.5.1.2 I2C Slave 10-bit Addressing Mode
In 10-bit Addressing mode, the first received byte is compared to the binary value of `1 1 1 1 0 A9 A8 0'. A9 and A8 are the two MSb of the 10-bit address and stored in bits 2 and 1 of the SSPxADD register. After the acknowledge of the high byte the UA bit is set and SCLx is held low until the user updates SSPxADD with the low address. The low address byte is clocked in and all 8 bits are compared to the low address value in SSPxADD. Even if there is not an address match; SSPxIF and UA are set, and SCLx is held low until SSPxADD is updated to receive a high byte again. When SSPxADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. A high and low address match as a write request is required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hardware will then acknowledge the read request and prepare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match.
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24.5.2 SLAVE RECEPTION 24.5.2.2 7-bit Reception with AHEN and DHEN When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and acknowledged. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF bit of the SSPxSTAT register is set, or bit SSPxOV bit of the SSPxCON1 register is set. The BOEN bit of the SSPxCON3 register modifies this operation. For more information see Register 24-4. An MSSPx interrupt is generated for each transferred data byte. Flag bit, SSPxIF, must be cleared by software. When the SEN bit of the SSPxCON2 register is set, SCLx will be held low (clock stretch) following each received byte. The clock must be released by setting the CKP bit of the SSPxCON1 register, except sometimes in 10-bit mode. See Section 24.2.3 "SPI Master Mode" for more detail. 24.5.2.1 7-bit Addressing Reception Slave device reception with AHEN and DHEN set operate the same as without these options with extra interrupts and clock stretching added after the 8th falling edge of SCLx. These additional interrupts allow the slave software to decide whether it wants to ACK the receive address or data byte, rather than the hardware. This functionality adds support for PMBusTM that was not present on previous versions of this module. This list describes the steps that need to be taken by slave software to use these options for I2C communication. Figure 24-15 displays a module using both address and data holding. Figure 24-16 includes the operation with the SEN bit of the SSPxCON2 register set. S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. 2. Matching address with R/W bit clear is clocked in. SSPxIF is set and CKP cleared after the 8th falling edge of SCLx. 3. Slave clears the SSPxIF. 4. Slave can look at the ACKTIM bit of the SSPxCON3 register to determine if the SSPxIF was after or before the ACK. 5. Slave reads the address value from SSPxBUF, clearing the BF flag. 6. Slave sets ACK value clocked out to the master by setting ACKDT. 7. Slave releases the clock by setting CKP. 8. SSPxIF is set after an ACK, not after a NACK. 9. If SEN = 1 the slave hardware will stretch the clock after the ACK. 10. Slave clears SSPxIF. Note: SSPxIF is still set after the 9th falling edge of SCLx even if there is no clock stretching and BF has been cleared. Only if NACK is sent to Master is SSPxIF not set 11. SSPxIF set and CKP cleared after 8th falling edge of SCLx for a received data byte. 12. Slave looks at ACKTIM bit of SSPxCON3 to determine the source of the interrupt. 13. Slave reads the received data from SSPxBUF clearing BF. 14. Steps 7-14 are the same for each received data byte. 15. Communication is ended by either the slave sending an ACK = 1, or the master sending a Stop condition. If a Stop is sent and Interrupt on Stop Detect is disabled, the slave will only know by polling the P bit of the SSTSTAT register. 1.
This section describes a standard sequence of events for the MSSPx module configured as an I2C Slave in 7-bit Addressing mode. All decisions made by hardware or software and their effect on reception. Figure 24-13 and Figure 24-14 is used as a visual reference for this description. This is a step by step process of what typically must be done to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Start bit detected. S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. Matching address with R/W bit clear is received. The slave pulls SDAx low sending an ACK to the master, and sets SSPxIF bit. Software clears the SSPxIF bit. Software reads received address from SSPxBUF clearing the BF flag. If SEN = 1; Slave software sets CKP bit to release the SCLx line. The master clocks out a data byte. Slave drives SDAx low sending an ACK to the master, and sets SSPxIF bit. Software clears SSPxIF. Software reads the received byte from SSPxBUF clearing BF. Steps 8-12 are repeated for all received bytes from the Master. Master sends Stop condition, setting P bit of SSPxSTAT, and the bus goes idle.
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Preliminary
DS41391C-page 249
FIGURE 24-14:
DS41391C-page 250
Bus Master sends Stop condition From Slave to Master Receiving Address A5 ACK A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 Receiving Data Receiving Data D0 ACK = 1 3 1 2 3 4 5 6 7 8 9 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Cleared by software Cleared by software SSPxIF set on 9th falling edge of SCLx SSPxBUF is read First byte of data is available in SSPxBUF SSPxOV set because SSPxBUF is still full. ACK is not sent.
PIC16F/LF1826/27
SDAx
A7
A6
SCLx
S
1
2
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)
Preliminary
SSPxIF
BF
SSPxOV
2010 Microchip Technology Inc.
FIGURE 24-15:
Bus Master sends Stop condition
2010 Microchip Technology Inc.
Receive Data A2 A1 R/W=0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 Receive Data D1 D0 ACK A4 A3 4 1 Clock is held low until CKP is set to `1' 2 3 4 5 6 7 8 9 5 6 7 8 9 SEN 1 2 3 SEN 4 5 6 7 8 9 P Cleared by software Cleared by software
falling edge of SCLx
Receive Address
SDAx
A7
A6
A5
SCLx
S
1
2
3
SSPxIF SSPxIF set on 9th
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)
Preliminary
SSPxBUF is read CKP is written to `1' in software, releasing SCLx
BF
First byte of data is available in SSPxBUF
SSPxOV SSPxOV set because SSPxBUF is still full. ACK is not sent.
CKP
PIC16F/LF1826/27
CKP is written to 1 in software, releasing SCLx
SCLx is not held low because ACK= 1
DS41391C-page 251
FIGURE 24-16:
Master Releases SDAx to slave for ACK sequence Receiving Data ACK ACK=1 D7 D6 D5 D4 D3 D2 D1 D0 Received Data
Master sends Stop condition
DS41391C-page 252 ACK D7 D6 D5 D4 D3 D2 D1 D0
3 1 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 4 5 6 7 8 9 9 P If AHEN = 1: SSPxIF is set SSPxIF is set on 9th falling edge of SCLx, after ACK Cleared by software Data is read from SSPxBUF No interrupt after not ACK from Slave Address is read from SSBUF Slave software clears ACKDT to ACK the received byte Slave software sets ACKDT to not ACK When DHEN=1: CKP is cleared by hardware on 8th falling edge of SCLx CKP set by software, SCLx is released ACKTIM cleared by hardware in 9th rising edge of SCLx ACKTIM set by hardware on 8th falling edge of SCLx
SDAx
Receiving Address
A7 A6 A5 A4 A3 A2 A1
SCLx
S
1
2
SSPxIF
PIC16F/LF1826/27
BF
ACKDT
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)
Preliminary
CKP
When AHEN=1: CKP is cleared by hardware and SCLx is stretched
ACKTIM
ACKTIM set by hardware on 8th falling edge of SCLx
S
2010 Microchip Technology Inc.
P
FIGURE 24-17:
Master sends Stop condition Receive Data ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
R/W = 0 ACK D7 D6 D5 D4 D3 D2 D1 D0 Receive Data
Master releases SDAx to slave for ACK sequence
2010 Microchip Technology Inc. 5 67 8 9 1 23 4 5 67 8 9 1 34 5 67 8 2 9
P Cleared by software No interrupt after if not ACK from Slave SSPxBUF can be read any time before next byte is loaded Received data is available on SSPxBUF Slave sends not ACK CKP is not cleared if not ACK Set by software, release SCLx When DHEN = 1; on the 8th falling edge of SCLx of a received data byte, CKP is cleared ACKTIM is cleared by hardware on 9th rising edge of SCLx
SDAx
Receiving Address
A7 A6 A5 A4 A3 A2 A1
SCLx
S
1
23
4
SSPxIF
BF
Received address is loaded into SSPxBUF
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)
Preliminary
ACKDT
Slave software clears ACKDT to ACK the received byte
CKP
When AHEN = 1; on the 8th falling edge of SCLx of an address byte, CKP is cleared
ACKTIM
ACKTIM is set by hardware on 8th falling edge of SCLx
S
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P
PIC16F/LF1826/27
24.5.3 SLAVE TRANSMISSION 24.5.3.2 7-bit Transmission
When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPxSTAT register is set. The received address is loaded into the SSPxBUF register, and an ACK pulse is sent by the slave on the ninth bit. Following the ACK, slave hardware clears the CKP bit and the SCLx pin is held low (see Section 24.5.6 "Clock Stretching" for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. The transmit data must be loaded into the SSPxBUF register which also loads the SSPxSR register. Then the SCLx pin should be released by setting the CKP bit of the SSPxCON1 register. The eight data bits are shifted out on the falling edge of the SCLx input. This ensures that the SDAx signal is valid during the SCLx high time. The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCLx input pulse. This ACK value is copied to the ACKSTAT bit of the SSPxCON2 register. If ACKSTAT is set (not ACK), then the data transfer is complete. In this case, when the not ACK is latched by the slave, the slave goes idle and waits for another occurrence of the Start bit. If the SDAx line was low (ACK), the next transmit data must be loaded into the SSPxBUF register. Again, the SCLx pin must be released by setting bit CKP. An MSSPx interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared by software and the SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the falling edge of the ninth clock pulse. A master device can transmit a read request to a slave, and then clock data out of the slave. The list below outlines what software for a slave will need to do to accomplish a standard transmission. Figure 24-17 can be used as a reference to this list. Master sends a Start condition on SDAx and SCLx. 2. S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. 3. Matching address with R/W bit set is received by the Slave setting SSPxIF bit. 4. Slave hardware generates an ACK and sets SSPxIF. 5. SSPxIF bit is cleared by user. 6. Software reads the received address from SSPxBUF, clearing BF. 7. R/W is set so CKP was automatically cleared after the ACK. 8. The slave software loads the transmit data into SSPxBUF. 9. CKP bit is set releasing SCLx, allowing the master to clock the data out of the slave. 10. SSPxIF is set after the ACK response from the master is loaded into the ACKSTAT register. 11. SSPxIF bit is cleared. 12. The slave software checks the ACKSTAT bit to see if the master wants to clock out more data. Note 1: If the master ACKs the clock will be stretched. 2: ACKSTAT is the only bit updated on the rising edge of SCLx (9th) rather than the falling. 13. Steps 9-13 are repeated for each transmitted byte. 14. If the master sends a not ACK; the clock is not held, but SSPxIF is still set. 15. The master sends a Restart condition or a Stop. 16. The slave is no longer addressed. 1.
24.5.3.1
Slave Mode Bus Collision
A slave receives a Read request and begins shifting data out on the SDAx line. If a bus collision is detected and the SBCDE bit of the SSPxCON3 register is set, the BCLxIF bit of the PIRx register is set. Once a bus collision is detected, the slave goes Idle and waits to be addressed again. User software can use the BCLxIF bit to handle a slave bus collision.
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FIGURE 24-18:
Master sends Stop condition
Receiving Address D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
Transmitting Data
Automatic
Transmitting Data
ACK
SDAx 2 3 4 5 6 7 8 9
A7 A6 A5 A4 A3 A2 A1
R/W = 1 Automatic ACK
SCLx
2010 Microchip Technology Inc.
P Cleared by software Received address is read from SSPxBUF Data to transmit is loaded into SSPxBUF BF is automatically cleared after 8th falling edge of SCLx When R/W is set SCLx is always held low after 9th SCLx falling edge Set by software CKP is not held for not ACK Masters not ACK is copied to ACKSTAT R/W is copied from the matching address byte Indicates an address has been received
S
1
SSPxIF
BF
CKP
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)
Preliminary
ACKSTAT
R/W
D/A
S
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P
PIC16F/LF1826/27
24.5.3.3 7-bit Transmission with Address Hold Enabled
Setting the AHEN bit of the SSPxCON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPxIF interrupt is set. Figure 24-18 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. Bus starts Idle. Master sends Start condition; the S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. 3. Master sends matching address with R/W bit set. After the 8th falling edge of the SCLx line the CKP bit is cleared and SSPxIF interrupt is generated. 4. Slave software clears SSPxIF. 5. Slave software reads ACKTIM bit of SSPxCON3 register, and R/W and D/A of the SSPxSTAT register to determine the source of the interrupt. 6. Slave reads the address value from the SSPxBUF register clearing the BF bit. 7. Slave software decides from this information if it wishes to ACK or not ACK and sets ACKDT bit of the SSPxCON2 register accordingly. 8. Slave sets the CKP bit releasing SCLx. 9. Master clocks in the ACK value from the slave. 10. Slave hardware automatically clears the CKP bit and sets SSPxIF after the ACK if the R/W bit is set. 11. Slave software clears SSPxIF. 12. Slave loads value to transmit to the master into SSPxBUF setting the BF bit. Note: SSPxBUF cannot be loaded until after the ACK. 13. Slave sets CKP bit releasing the clock. 14. Master clocks out the data from the slave and sends an ACK value on the 9th SCLx pulse. 15. Slave hardware copies the ACK value into the ACKSTAT bit of the SSPxCON2 register. 16. Steps 10-15 are repeated for each byte transmitted to the master from the slave. 17. If the master sends a not ACK the slave releases the bus allowing the master to send a Stop and end the communication. Note: Master must send a not ACK on the last byte to ensure that the slave releases the SCLx line to receive a Stop. 1. 2.
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FIGURE 24-19:
Master sends Stop condition
Master releases SDAx to slave for ACK sequence R/W = 1 ACK 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 D7 D6 D5 D4 D3 D2 D1 D0 8 9 Automatic Transmitting Data ACK
Receiving Address
SDAx 3 4 5 6 7
A7 A6 A5 A4 A3 A2 A1
Transmitting Data Automatic D7 D6 D5 D4 D3 D2 D1 D0 ACK
2010 Microchip Technology Inc.
P Cleared by software Received address is read from SSPxBUF Data to transmit is loaded into SSPxBUF BF is automatically cleared after 8th falling edge of SCLx Slave clears ACKDT to ACK address Master's ACK response is copied to SSPxSTAT CKP not cleared When R/W = 1; CKP is always cleared after ACK Set by software, releases SCLx after not ACK ACKTIM is cleared on 9th rising edge of SCLx
SCLx
S
1
2
SSPxIF
BF
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)
Preliminary
ACKDT
ACKSTAT
CKP
When AHEN = 1; CKP is cleared by hardware after receiving matching address.
ACKTIM
ACKTIM is set on 8th falling edge of SCLx
R/W
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D/A
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24.5.4 SLAVE MODE 10-BIT ADDRESS RECEPTION 24.5.5 10-BIT ADDRESSING WITH ADDRESS OR DATA HOLD This section describes a standard sequence of events for the MSSPx module configured as an I2C Slave in 10-bit Addressing mode. Figure 24-19 is used as a visual reference for this description. This is a step by step process of what must be done by slave software to accomplish I2C communication. 1. 2. Bus starts Idle. Master sends Start condition; S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. Master sends matching high address with R/W bit clear; UA bit of the SSPxSTAT register is set. Slave sends ACK and SSPxIF is set. Software clears the SSPxIF bit. Software reads received address from SSPxBUF clearing the BF flag. Slave loads low address into SSPxADD, releasing SCLx. Master sends matching low address byte to the Slave; UA bit is set. Note: Updates to the SSPxADD register are not allowed until after the ACK sequence. 9. Slave sends ACK and SSPxIF is set. Note: If the low address does not match, SSPxIF and UA are still set so that the slave software can set SSPxADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. Slave clears SSPxIF. 11. Slave reads the received matching address from SSPxBUF clearing BF. 12. Slave loads high address into SSPxADD. 13. Master clocks a data byte to the slave and clocks out the slaves ACK on the 9th SCLx pulse; SSPxIF is set. 14. If SEN bit of SSPxCON2 is set, CKP is cleared by hardware and the clock is stretched. 15. Slave clears SSPxIF. 16. Slave reads the received byte from SSPxBUF clearing BF. 17. If SEN is set the slave sets CKP to release the SCLx. 18. Steps 13-17 repeat for each received byte. 19. Master sends Stop to end the transmission. Reception using 10-bit addressing with AHEN or DHEN set is the same as with 7-bit modes. The only difference is the need to update the SSPxADD register using the UA bit. All functionality, specifically when the CKP bit is cleared and SCLx line is held low are the same. Figure 24-20 can be used as a reference of a slave in 10-bit addressing with AHEN set. Figure 24-21 shows a standard waveform for a slave transmitter in 10-bit Addressing mode.
3. 4. 5. 6. 7. 8.
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Preliminary
2010 Microchip Technology Inc.
FIGURE 24-20:
Master sends Stop condition
2010 Microchip Technology Inc.
Receive Second Address Byte Receive Data D7 D6 D5 D4 D3 D2 D1 D0 ACK ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK Receive Data D7 D6 D5 D4 D3 D2 D1 D0 ACK 0 A9 A8 5 6 7 8 9 1 2 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 3 4 5 6 7 8 9 P SCLx is held low while CKP = 0 Cleared by software Receive address is read from SSPxBUF Data is read from SSPxBUF Software updates SSPxADD and releases SCLx Set by software, When SEN = 1; releasing SCLx CKP is cleared after 9th falling edge of received byte
Receive First Address Byte
SDAx
1
1
1
1
SCLx
S
1
2
3
4
SSPxIF
Set by hardware on 9th falling edge
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)
Preliminary
BF
If address matches SSPxADD it is loaded into SSPxBUF
UA
When UA = 1; SCLx is held low
PIC16F/LF1826/27
CKP
DS41391C-page 259
FIGURE 24-21:
Receive First Address Byte R/W = 0 A8 ACK ACK A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 Receive Second Address Byte Receive Data
Receive Data D6 D5
DS41391C-page 260
1 0
A9 4 UA UA 5 6 7 8 9 1 2 9 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 1 2 Set by hardware on 9th falling edge Cleared by software Cleared by software SSPxBUF can be read anytime before the next received byte Received data is read from SSPxBUF Update to SSPxADD is not allowed until 9th falling edge of SCLx Update of SSPxADD, clears UA and releases SCLx Set CKP with software releases SCLx
SDAx
1
1
1
SCLx
S
1
2
3
PIC16F/LF1826/27
SSPxIF
BF
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)
Preliminary
ACKDT
Slave software clears ACKDT to ACK the received byte
UA
CKP
If when AHEN = 1; on the 8th falling edge of SCLx of an address byte, CKP is cleared
ACKTIM
2010 Microchip Technology Inc.
ACKTIM is set by hardware on 8th falling edge of SCLx
FIGURE 24-22:
Master sends Stop condition
2010 Microchip Technology Inc.
Master sends Restart event Receiving Second Address Byte Receive First Address Byte A7 A6 A5 A4 A3 A2 A1 A0 ACK Transmitting Data Byte ACK D7 D6 D5 D4 D3 D2 D1 D0 Master sends not ACK ACK = 1
SDAx
Receiving Address R/W = 0 1 1 1 1 0 A9 A8 ACK
1 1 1 1 0 A9 A8
SCLx 5 1 2 Sr 3 4 5 6 78 9 23 4 5 6 78 9 6 1 1 7 8 9
S
1
2
3
4
2
3
4
5
6
7
8
9
P
SSPxIF Cleared by software Set by hardware
Set by hardware
BF Received address is read from SSPxBUF High address is loaded back into SSPxADD Data to transmit is loaded into SSPxBUF
I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)
Preliminary
After SSPxADD is updated, UA is cleared and SCLx is released When R/W = 1; CKP is cleared on 9th falling edge of SCLx R/W is copied from the matching address byte
SSPxBUF loaded with received address
UA
UA indicates SSPxADD must be updated
CKP
ACKSTAT
Set by software releases SCLx
Masters not ACK is copied
R/W
D/A
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Indicates an address has been received
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24.5.6 CLOCK STRETCHING 24.5.6.2 10-bit Addressing Mode Clock stretching occurs when a device on the bus holds the SCLx line low effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any stretching done by a slave is invisible to the master software and handled by the hardware that generates SCLx. The CKP bit of the SSPxCON1 register is used to control stretching in software. Any time the CKP bit is cleared, the module will wait for the SCLx line to go low and then hold it. Setting CKP will release SCLx and allow more communication. 24.5.6.1 Normal Clock Stretching In 10-bit Addressing mode, when the UA bit is set, the clock is always stretched. This is the only time the SCLx is stretched without CKP being cleared. SCLx is released immediately after a write to SSPxADD. Note: Previous versions of the module did not stretch the clock if the second address byte did not match. 24.5.6.3 Byte NACKing
When AHEN bit of SSPxCON3 is set; CKP is cleared by hardware after the 8th falling edge of SCLx for a received matching address byte. When DHEN bit of SSPxCON3 is set; CKP is cleared after the 8th falling edge of SCLx for received data. Stretching after the 8th falling edge of SCLx allows the slave to look at the received address or data and decide if it wants to ACK the received data. 24.5.7 CLOCK SYNCHRONIZATION AND THE CKP BIT
Following an ACK if the R/W bit of SSPxSTAT is set, a read request, the slave hardware will clear CKP. This allows the slave time to update SSPxBUF with data to transfer to the master. If the SEN bit of SSPxCON2 is set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready; CKP is set by software and communication resumes. Note 1: The BF bit has no effect on if the clock will be stretched or not. This is different than previous versions of the module that would not stretch the clock, clear CKP, if SSPxBUF was read before the 9th falling edge of SCLx. 2: Previous versions of the module did not stretch the clock for a transmission if SSPxBUF was loaded before the 9th falling edge of SCLx. It is now always cleared for read requests.
Any time the CKP bit is cleared, the module will wait for the SCLx line to go low and then hold it. However, clearing the CKP bit will not assert the SCLx output low until the SCLx output is already sampled low. Therefore, the CKP bit will not assert the SCLx line until an external I2C master device has already asserted the SCLx line. The SCLx output will remain low until the CKP bit is set and all other devices on the I2C bus have released SCLx. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCLx (see Figure 24-22).
FIGURE 24-23:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDAx
DX
DX - 1
SCLx
CKP
Master device asserts clock Master device releases clock
WR SSPxCON1
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24.5.8 GENERAL CALL ADDRESS SUPPORT The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an acknowledge. The general call address is a reserved address in the I2C protocol, defined as address 0x00. When the GCEN bit of the SSPxCON2 register is set, the slave module will automatically ACK the reception of this address regardless of the value stored in SSPxADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave software can read SSPxBUF and respond. Figure 24-23 shows a general call reception sequence. In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. If the AHEN bit of the SSPxCON3 register is set, just as with any other address reception, the slave hardware will stretch the clock after the 8th falling edge of SCLx. The slave must then set its ACKDT value and release the clock with communication progressing as it would normally.
FIGURE 24-24:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 Receiving Data D6 D5 D4 D3 D2 D1 D0 ACK
SDAx SCLx S SSPxIF BF (SSPxSTAT<0>)
General Call Address
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Cleared by software GCEN (SSPxCON2<7>) SSPxBUF is read '1'
24.5.9
SSPX MASK REGISTER
An SSPx Mask (SSPxMSK) register (Register 24-5) is available in I2C Slave mode as a mask for the value held in the SSPxSR register during an address comparison operation. A zero (`0') bit in the SSPxMSK register has the effect of making the corresponding bit of the received address a "don't care". This register is reset to all `1's upon any Reset condition and, therefore, has no effect on standard SSPx operation until written with a mask value. The SSPx Mask register is active during: * 7-bit Address mode: address compare of A<7:1>. * 10-bit Address mode: address compare of A<7:0> only. The SSPx mask has no effect during the reception of the first (high) byte of the address.
2010 Microchip Technology Inc.
Preliminary
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24.6 I2C MASTER MODE
24.6.1 I2C MASTER MODE OPERATION Master mode is enabled by setting and clearing the appropriate SSPxM bits in the SSPxCON1 register and by setting the SSPxEN bit. In Master mode, the SCLx and SDAx lines are set as inputs and are manipulated by the MSSPx hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSPx module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is Idle. In Firmware Controlled Master mode, user code conducts all I 2C bus operations based on Start and Stop bit condition detection. Start and Stop condition detection is the only active circuitry in this mode. All other communication is done by the user software directly manipulating the SDAx and SCLx lines. The following events will cause the SSPx Interrupt Flag bit, SSPxIF, to be set (SSPx interrupt, if enabled): * * * * * Start condition detected Stop condition detected Data transfer byte transmitted/received Acknowledge transmitted/received Repeated Start generated Note 1: The MSSPx module, when configured in I2C Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPxBUF register to initiate transmission before the Start condition is complete. In this case, the SSPxBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPxBUF did not occur 2: When in Master mode, Start/Stop detection is masked and an interrupt is generated when the SEN/PEN bit is cleared and the generation is complete. The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDAx, while SCLx outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic `0'. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic `1'. Thus, the first byte transmitted is a 7-bit slave address followed by a `1' to indicate the receive bit. Serial data is received via SDAx, while SCLx outputs the serial clock. Serial data is received 8 bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. A Baud Rate Generator is used to set the clock frequency output on SCLx. See Section 24.7 "Baud Rate Generator" for more detail.
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24.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCLx pin (SCLx allowed to float high). When the SCLx pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and begins counting. This ensures that the SCLx high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 24-25).
FIGURE 24-25:
SDAx
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
DX SCLx deasserted but slave holds SCLx low (clock arbitration) DX - 1 SCLx allowed to transition high
SCLx BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h
SCLx is sampled high, reload takes place and BRG starts its count BRG Reload
24.6.3
WCOL STATUS FLAG
If the user writes the SSPxBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). Any time the WCOL bit is set it indicates that an action on SSPxBUF was attempted while the module was not Idle. Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSPxCON2 is disabled until the Start condition is complete.
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Preliminary
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24.6.4 I2C MASTER MODE START
CONDITION TIMING
To initiate a Start condition, the user sets the Start Enable bit, SEN bit of the SSPxCON2 register. If the SDAx and SCLx pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and starts its count. If SCLx and SDAx are both sampled high when the Baud Rate Generator times out (TBRG), the SDAx pin is driven low. The action of the SDAx being driven low while SCLx is high is the Start condition and causes the S bit of the SSPxSTAT1 register to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit of the SSPxCON2 register will be automatically cleared
by hardware; the Baud Rate Generator is suspended, leaving the SDAx line held low and the Start condition is complete. Note 1: If at the beginning of the Start condition, the SDAx and SCLx pins are already sampled low, or if during the Start condition, the SCLx line is sampled low before the SDAx line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLxIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. 2: The Philips I2C Specification states that a bus collision cannot occur on a Start.
FIGURE 24-26:
FIRST START BIT TIMING
Write to SEN bit occurs here SDAx = 1, SCLx = 1 TBRG SDAx TBRG Set S bit (SSPxSTAT<3>) At completion of Start bit, hardware clears SEN bit and sets SSPxIF bit Write to SSPxBUF occurs here 1st bit TBRG SCLx S TBRG 2nd bit
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24.6.5 I2C MASTER MODE REPEATED
START CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit of the SSPxCON2 register is programmed high and the Master state machine is no longer active. When the RSEN bit is set, the SCLx pin is asserted low. When the SCLx pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDAx pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDAx is sampled high, the SCLx pin will be deasserted (brought high). When SCLx is sampled high, the Baud Rate Generator is reloaded and begins counting. SDAx and SCLx must be sampled high for one TBRG. This action is then followed by assertion of the SDAx pin (SDAx = 0) for one TBRG while SCLx is high. SCLx is asserted low. Following this, the RSEN bit of the
SSPxCON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDAx pin held low. As soon as a Start condition is detected on the SDAx and SCLx pins, the S bit of the SSPxSTAT register will be set. The SSPxIF bit will not be set until the Baud Rate Generator has timed out. Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated Start condition occurs if: * SDAx is sampled low when SCLx goes from low-to-high. * SCLx goes low before SDAx is asserted low. This may indicate that another master is attempting to transmit a data `1'.
FIGURE 24-27:
REPEAT START CONDITION WAVEFORM
Write to SSPxCON2 occurs here SDAx = 1, SCLx (no change) TBRG SDAx S bit set by hardware SDAx = 1, SCLx = 1 TBRG TBRG 1st bit At completion of Start bit, hardware clears RSEN bit and sets SSPxIF
Write to SSPxBUF occurs here TBRG SCLx Sr Repeated Start TBRG
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24.6.6 I2C MASTER MODE TRANSMISSION
24.6.6.3
ACKSTAT Status Flag
Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDAx pin after the falling edge of SCLx is asserted. SCLx is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCLx is released high. When the SCLx pin is released high, it is held that way for TBRG. The data on the SDAx pin must remain stable for that duration and some hold time after the next falling edge of SCLx. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDAx. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKSTAT bit on the rising edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSPxIF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSPxBUF, leaving SCLx low and SDAx unchanged (Figure 24-27). After the write to the SSPxBUF, each bit of the address will be shifted out on the falling edge of SCLx until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will release the SDAx pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDAx pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT Status bit of the SSPxCON2 register. Following the falling edge of the ninth clock transmission of the address, the SSPxIF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPxBUF takes place, holding SCLx low and allowing SDAx to float.
In Transmit mode, the ACKSTAT bit of the SSPxCON2 register is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 24.6.6.4 1. 2. 3. 4. 5. 6. Typical transmit sequence:
7.
8.
9. 10. 11.
12. 13.
24.6.6.1
BF Status Flag
The user generates a Start condition by setting the SEN bit of the SSPxCON2 register. SSPxIF is set by hardware on completion of the Start. SSPxIF is cleared by software. The MSSPx module will wait the required start time before any other operation takes place. The user loads the SSPxBUF with the slave address to transmit. Address is shifted out the SDAx pin until all 8 bits are transmitted. Transmission begins as soon as SSPxBUF is written to. The MSSPx module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPxCON2 register. The MSSPx module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. The user loads the SSPxBUF with eight bits of data. Data is shifted out the SDAx pin until all 8 bits are transmitted. The MSSPx module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPxCON2 register. Steps 8-11 are repeated for all transmitted data bytes. The user generates a Stop or Restart condition by setting the PEN or RSEN bits of the SSPxCON2 register. Interrupt is generated once the Stop/Restart condition is complete.
In Transmit mode, the BF bit of the SSPxSTAT register is set when the CPU writes to SSPxBUF and is cleared when all 8 bits are shifted out.
24.6.6.2
WCOL Status Flag
If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPxSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). WCOL must be cleared by software before the next transmission.
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2010 Microchip Technology Inc.
FIGURE 24-28:
Write SSPxCON2<0> SEN = 1 Start condition begins From slave, clear ACKSTAT bit SSPxCON2<6>
R/W = 0
ACKSTAT in SSPxCON2 = 1
2010 Microchip Technology Inc.
SEN = 0 Transmit Address to Slave SDAx A7 SSPxBUF written with 7-bit address and R/W start transmit SCLx S 1 2 3 4 5 6 7 8 9 1 SCLx held low while CPU responds to SSPxIF 2 3 4 5 6 7 8 9 P A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 Transmitting Data or Second Half of 10-bit Address D1 D0 ACK SSPxIF Cleared by software Cleared by software service routine from SSPx interrupt Cleared by software BF (SSPxSTAT<0>) SSPxBUF written SEN After Start condition, SEN cleared by hardware SSPxBUF is written by software PEN R/W
I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
Preliminary
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24.6.7 I2C MASTER MODE RECEPTION
24.6.7.4 1. 2. 3. 4. 5. Typical Receive Sequence: Master mode reception is enabled by programming the Receive Enable bit, RCEN bit of the SSPxCON2 register. Note: The MSSPx module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The user generates a Start condition by setting the SEN bit of the SSPxCON2 register. SSPxIF is set by hardware on completion of the Start. SSPxIF is cleared by software. User writes SSPxBUF with the slave address to transmit and the R/W bit set. Address is shifted out the SDAx pin until all 8 bits are transmitted. Transmission begins as soon as SSPxBUF is written to. The MSSPx module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPxCON2 register. The MSSPx module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. User sets the RCEN bit of the SSPxCON2 register and the Master clocks in a byte from the slave. After the 8th falling edge of SCLx, SSPxIF and BF are set. Master clears SSPxIF and reads the received byte from SSPxUF, clears BF. Master sets ACK value sent to slave in ACKDT bit of the SSPxCON2 register and initiates the ACK by setting the ACKEN bit. Masters ACK is clocked out to the Slave and SSPxIF is set. User clears SSPxIF. Steps 8-13 are repeated for each received byte from the slave. Master sends a not ACK or Stop to end communication.
The Baud Rate Generator begins counting and on each rollover, the state of the SCLx pin changes (high-to-low/low-to-high) and data is shifted into the SSPxSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPxSR are loaded into the SSPxBUF, the BF flag bit is set, the SSPxIF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCLx low. The MSSPx is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable, ACKEN bit of the SSPxCON2 register.
6.
7.
8. 9. 10. 11.
24.6.7.1
BF Status Flag
In receive operation, the BF bit is set when an address or data byte is loaded into SSPxBUF from SSPxSR. It is cleared when the SSPxBUF register is read.
24.6.7.2
SSPxOV Status Flag
12. 13. 14. 15.
In receive operation, the SSPxOV bit is set when 8 bits are received into the SSPxSR and the BF flag bit is already set from a previous reception.
24.6.7.3
WCOL Status Flag
If the user writes the SSPxBUF when a receive is already in progress (i.e., SSPxSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur).
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Preliminary
2010 Microchip Technology Inc.
FIGURE 24-29:
Write to SSPxCON2<0>(SEN = 1), begin Start condition Master configured as a receiver by programming SSPxCON2<3> (RCEN = 1) RCEN cleared automatically Receiving Data from Slave ACK Receiving Data from Slave RCEN = 1, start next receive RCEN cleared automatically ACK ACK from Master SDAx = ACKDT = 0 Set ACKEN, start Acknowledge sequence SDAx = ACKDT = 1 PEN bit = 1 written here
Write to SSPxCON2<4> to start Acknowledge sequence SDAx = ACKDT (SSPxCON2<5>) = 0
SEN = 0 Write to SSPxBUF occurs here, ACK from Slave start XMIT R/W = 1
2010 Microchip Technology Inc.
A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
ACK ACK is not sent Bus master terminates transfer
Transmit Address to Slave
SDAx
A7
A6 A5 A4 A3 A2
SCLx
Set SSPxIF interrupt at end of receive
S
1 5 1 2 3 4 5 1 2 3 4 5 6
2
3 4 8 6 7 8 9
6 9
7
7
8
9
Set SSPxIF at end of receive
P
Set SSPxIF interrupt at end of Acknowledge sequence
Data shifted in on falling edge of CLK
SSPxIF
Cleared by software Cleared by software
Set SSPxIF interrupt at end of Acknowledge sequence Cleared by software Cleared in software
I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
Preliminary
Master configured as a receiver by programming SSPxCON2<3> (RCEN = 1) RCEN cleared automatically ACK from Master SDAx = ACKDT = 0
SDAx = 0, SCLx = 1 while CPU responds to SSPxIF
Cleared by software
Set P bit (SSPxSTAT<4>) and SSPxIF
BF (SSPxSTAT<0>)
Last bit is shifted into SSPxSR and contents are unloaded into SSPxBUF
SSPxOV
SSPxOV is set because SSPxBUF is still full
ACKEN
RCEN
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RCEN cleared automatically
PIC16F/LF1826/27
24.6.8 ACKNOWLEDGE SEQUENCE TIMING 24.6.9 STOP CONDITION TIMING
An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN bit of the SSPxCON2 register. When this bit is set, the SCLx pin is pulled low and the contents of the Acknowledge data bit are presented on the SDAx pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCLx pin is deasserted (pulled high). When the SCLx pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCLx pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSPx module then goes into Idle mode (Figure 24-29). A Stop bit is asserted on the SDAx pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSPxCON2 register. At the end of a receive/transmit, the SCLx line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDAx line low. When the SDAx line is sampled low, the Baud Rate Generator is reloaded and counts down to `0'. When the Baud Rate Generator times out, the SCLx pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDAx pin will be deasserted. When the SDAx pin is sampled high while SCLx is high, the P bit of the SSPxSTAT register is set. A TBRG later, the PEN bit is cleared and the SSPxIF bit is set (Figure 24-30).
24.6.9.1
WCOL Status Flag
24.6.8.1
WCOL Status Flag
If the user writes the SSPxBUF when an Acknowledge sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn't occur).
If the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur).
FIGURE 24-30:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here, write to SSPxCON2 ACKEN = 1, ACKDT = 0 TBRG SDAx SCLx D0 8 ACK TBRG ACKEN automatically cleared
9
SSPxIF SSPxIF set at the end of receive Note: TBRG = one Baud Rate Generator period. Cleared in software SSPxIF set at the end of Acknowledge sequence
Cleared in software
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FIGURE 24-31: STOP CONDITION RECEIVE OR TRANSMIT MODE
SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG after SDAx sampled high. P bit (SSPxSTAT<4>) is set. PEN bit (SSPxCON2<2>) is cleared by hardware and the SSPxIF bit is set TBRG Write to SSPxCON2, set PEN Falling edge of 9th clock SCLx
SDAx
ACK P TBRG TBRG TBRG SCLx brought high after TBRG SDAx asserted low before rising edge of clock to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
24.6.10
SLEEP OPERATION
the I2C slave
24.6.13
While in Sleep mode, module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSPx interrupt is enabled).
MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION
24.6.11
EFFECTS OF A RESET
A Reset disables the MSSPx module and terminates the current transfer.
24.6.12
MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSPx module is disabled. Control of the I 2C bus may be taken when the P bit of the SSPxSTAT register is set, or the bus is Idle, with both the S and P bits clear. When the bus is busy, enabling the SSPx interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDAx line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed by hardware with the result placed in the BCLxIF bit. The states where arbitration can be lost are: * * * * * Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDAx pin, arbitration takes place when the master outputs a `1' on SDAx, by letting SDAx float high and another master asserts a `0'. When the SCLx pin floats high, data should be stable. If the expected data on SDAx is a `1' and the data sampled on the SDAx pin is `0', then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLxIF and reset the I2C port to its Idle state (Figure 24-31). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDAx and SCLx lines are deasserted and the SSPxBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDAx and SCLx lines are deasserted and the respective control bits in the SSPxCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. The master will continue to monitor the SDAx and SCLx pins. If a Stop condition occurs, the SSPxIF bit will be set. A write to the SSPxBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPxSTAT register, or the bus is Idle and the S and P bits are cleared.
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FIGURE 24-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Data changes while SCLx = 0 SDAx line pulled low by another source SDAx released by master SDAx Sample SDAx. While SCLx is high, data doesn't match what is driven by the master. Bus collision has occurred.
SCLx
Set bus collision interrupt (BCLxIF)
BCLxIF
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24.6.13.1 Bus Collision During a Start Condition
During a Start condition, a bus collision occurs if: a) b) SDAx or SCLx are sampled low at the beginning of the Start condition (Figure 24-32). SCLx is sampled low before SDAx is asserted low (Figure 24-33). If the SDAx pin is sampled low during this count, the BRG is reset and the SDAx line is asserted early (Figure 24-34). If, however, a `1' is sampled on the SDAx pin, the SDAx pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to zero; if the SCLx pin is sampled as `0' during this time, a bus collision does not occur. At the end of the BRG count, the SCLx pin is asserted low. Note: The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDAx before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions.
During a Start condition, both the SDAx and the SCLx pins are monitored. If the SDAx pin is already low, or the SCLx pin is already low, then all of the following occur: * the Start condition is aborted, * the BCLxIF flag is set and * the MSSPx module is reset to its Idle state (Figure 24-32). The Start condition begins with the SDAx and SCLx pins deasserted. When the SDAx pin is sampled high, the Baud Rate Generator is loaded and counts down. If the SCLx pin is sampled low while SDAx is high, a bus collision occurs because it is assumed that another master is attempting to drive a data `1' during the Start condition.
FIGURE 24-33:
BUS COLLISION DURING START CONDITION (SDAX ONLY)
SDAx goes low before the SEN bit is set. Set BCLxIF, S bit and SSPxIF set because SDAx = 0, SCLx = 1.
SDAx
SCLx Set SEN, enable Start condition if SDAx = 1, SCLx = 1 SEN SDAx sampled low before Start condition. Set BCLxIF. S bit and SSPxIF set because SDAx = 0, SCLx = 1. SSPxIF and BCLxIF are cleared by software S SEN cleared automatically because of bus collision. SSPx module reset into Idle state.
BCLxIF
SSPxIF SSPxIF and BCLxIF are cleared by software
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FIGURE 24-34: BUS COLLISION DURING START CONDITION (SCLX = 0)
SDAx = 0, SCLx = 1
TBRG TBRG
SDAx Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF. BCLxIF Interrupt cleared by software S SSPxIF
SCLx
SEN
'0' '0'
'0' '0'
FIGURE 24-35:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDAx = 0, SCLx = 1 Set S Less than TBRG Set SSPxIF
TBRG
SDAx
SDAx pulled low by other master. Reset BRG and assert SDAx. S SCLx pulled low after BRG time-out Set SEN, enable Start sequence if SDAx = 1, SCLx = 1
SCLx
SEN
BCLxIF
'0'
S
SSPxIF SDAx = 0, SCLx = 1, set SSPxIF Interrupts cleared by software
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24.6.13.2 Bus Collision During a Repeated Start Condition
During a Repeated Start condition, a bus collision occurs if: a) b) A low level is sampled on SDAx when SCLx goes from low level to high level. SCLx goes low before SDAx is asserted low, indicating that another master is attempting to transmit a data `1'. If SDAx is low, a bus collision has occurred (i.e., another master is attempting to transmit a data `0', Figure 24-35). If SDAx is sampled high, the BRG is reloaded and begins counting. If SDAx goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDAx at exactly the same time. If SCLx goes from high-to-low before the BRG times out and SDAx has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data `1' during the Repeated Start condition, see Figure 24-36. If, at the end of the BRG time-out, both SCLx and SDAx are still high, the SDAx pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCLx pin, the SCLx pin is driven low and the Repeated Start condition is complete.
When the user releases SDAx and the pin is allowed to float high, the BRG is loaded with SSPxADD and counts down to zero. The SCLx pin is then deasserted and when sampled high, the SDAx pin is sampled.
FIGURE 24-36:
SDAx
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SCLx Sample SDAx when SCLx goes high. If SDAx = 0, set BCLxIF and release SDAx and SCLx. RSEN
BCLxIF Cleared by software S SSPxIF
'0' '0'
FIGURE 24-37:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG TBRG
SDAx SCLx SCLx goes low before SDAx, set BCLxIF. Release SDAx and SCLx. Interrupt cleared by software RSEN S SSPxIF
BCLxIF
'0'
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Preliminary
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24.6.13.3 Bus Collision During a Stop Condition
Bus collision occurs during a Stop condition if: a) After the SDAx pin has been deasserted and allowed to float high, SDAx is sampled low after the BRG has timed out. After the SCLx pin is deasserted, SCLx is sampled low before SDAx goes high. The Stop condition begins with SDAx asserted low. When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD and counts down to 0. After the BRG times out, SDAx is sampled. If SDAx is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data `0' (Figure 24-37). If the SCLx pin is sampled low before SDAx is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data `0' (Figure 24-38).
b)
FIGURE 24-38:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
TBRG TBRG TBRG SDAx sampled low after TBRG, set BCLxIF
SDAx SDAx asserted low SCLx PEN BCLxIF P SSPxIF
'0' '0'
FIGURE 24-39:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG TBRG TBRG
SDAx Assert SDAx SCLx PEN BCLxIF P SSPxIF SCLx goes low before SDAx goes high, set BCLxIF
'0' '0'
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TABLE 24-3:
Name INTCON PIE1 PIE2 PIE4(1) PIR1 PIR2 PIR4(1) TRISA TRISB SSPxADD SSPxBUF SSPxCON1 SSPxCON2 SSPxCON3 SSPxMSK SSPxSTAT Legend: * Note 1:
REGISTERS ASSOCIATED WITH I2CTM OPERATION
Bit 7 GIE Bit 6 PEIE ADIE C2IE -- ADIF C2IF -- TRISA6 TRISB6 ADD6 SSPOV ACKSTAT PCIE MSK6 CKE Bit 5 TMR0IE RCIE C1IE -- RCIF C1IF -- TRISA5 TRISB5 ADD5 SSPEN ACKDT SCIE MSK5 D/A Bit 4 INTE TXIE EEIE -- TXIF EEIF -- TRISA4 TRISB4 ADD4 CKP ACKEN BOEN MSK4 P Bit 3 IOCIE SSP1IE BCL1IE -- SSP1IF BCL1IF -- TRISA3 TRISB3 ADD3 SSPM3 RCEN SDAHT MSK3 S Bit 2 TMR0IF CCP1IE -- -- CCP1IF -- -- TRISA2 TRISB2 ADD2 SSPM2 PEN SBCDE MSK2 R/W Bit 1 INTF TMR2IE -- BCL2IE TMR2IF -- BCL2IF TRISA1 TRISB1 ADD1 SSPM1 RSEN AHEN MSK1 UA Bit 0 IOCIF TMR1IE CCP2IE(1) SSP2IE TMR1IF CCP2IF(1) SSP2IF TRISA0 TRISB0 ADD0 SSPM0 SEN DHEN MSK0 BF Reset Values on Page: 91 92 93 95 96 97 99 124 129 286 237* 283 284 285 286 282
TMR1GIE OSFIE -- TMR1GIF OSFIF -- TRISA7 TRISB7 ADD7 WCOL GCEN ACKTIM MSK7 SMP
MSSPx Receive Buffer/Transmit Register
-- = unimplemented, read as `0'. Shaded cells are not used by the MSSP module in I2CTM mode. Page provides register information. PIC16F/LF1827 only.
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24.7 BAUD RATE GENERATOR
The MSSPx module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPxADD register (Register 24-6). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. An internal signal "Reload" in Figure 24-39 triggers the value from SSPxADD to be loaded into the BRG counter. This occurs twice for each oscillation of the module clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSPx is being operated in. Table 24-4 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD.
EQUATION 24-1: FOSC FCLOCK = ------------------------------------------------ SSPxADD + 1 4
FIGURE 24-40:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPxM<3:0> SSPxADD<7:0>
SSPxM<3:0> SCLx
Reload Control SSPxCLK
Reload
BRG Down Counter
FOSC/2
Note: Values of 0x00, 0x01 and 0x02 are not valid for SSPxADD when used as a Baud Rate Generator for I2C. This is an implementation limitation.
TABLE 24-4:
FOSC
MSSPX CLOCK RATE W/BRG
FCY 8 MHz 8 MHz 8 MHz 4 MHz 4 MHz 4 MHz 1 MHz I2C BRG Value 13h 19h 4Fh 09h 0Ch 27h 09h FCLOCK (2 Rollovers of BRG) 400 kHz(1) 308 kHz 100 kHz 400 kHz(1) 308 kHz 100 kHz 100 kHz
32 MHz 32 MHz 32 MHz 16 MHz 16 MHz 16 MHz 4 MHz Note 1:
2C
specification (which applies to rates greater than The I interface does not conform to the 400 kHz 100 kHz) in all details, but may be used with care where higher rates are required by the application.
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24.7.1 ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function registers, APFCON0 and APFCON1. To determine which pins can be moved and what their default locations are upon a Reset, see Section 12.1 "Alternate Pin Function" for more information.
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REGISTER 24-1:
R/W-0/0 SMP bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared SMP: SPI Data Input Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I2 C Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select bit (SPI mode only) In SPI Master or Slave mode: 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state In I2 CTM mode only: 1 = Enable input logic so that thresholds are compliant with SM busTM specification 0 = Disable SM busTM specific inputs bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: Stop bit (I2C mode only. This bit is cleared when the MSSPx module is disabled, SSPxEN is cleared.) 1 = Indicates that a Stop bit has been detected last (this bit is `0' on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (I2C mode only. This bit is cleared when the MSSPx module is disabled, SSPxEN is cleared.) 1 = Indicates that a Start bit has been detected last (this bit is `0' on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. In I2 C Slave mode: 1 = Read 0 = Write In I2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Idle mode. bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPxADD register 0 = Address does not need to be updated BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSPxBUF is full 0 = Receive not complete, SSPxBUF is empty Transmit (I2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
SSPxSTAT: SSPx STATUS REGISTER
R/W-0/0 CKE R-0/0 D/A R-0/0 P R-0/0 S R-0/0 R/W R-0/0 UA R-0/0 BF bit 0
bit 4
bit 0
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REGISTER 24-2:
R/C/HS-0/0 WCOL bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets HS = Bit is set by hardware C = User cleared
SSPxCON1: SSPx CONTROL REGISTER 1
R/W-0/0 SSPxEN R/W-0/0 CKP R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 bit 0 SSPxOV SSPxM<3:0>
R/C/HS-0/0
WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSPxBUF register was attempted while the I2CTM conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision SSPxOV: Receive Overflow Indicator bit(1) In SPI mode: 1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPxBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register (must be cleared in software). 0 = No overflow 2C mode: In I 1 = A byte is received while the SSPxBUF register is still holding the previous byte. SSPxOV is a "don't care" in Transmit mode (must be cleared in software). 0 = No overflow SSPxEN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output In SPI mode: 1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as the source of the serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins In I2C mode: 1 = Enables the serial port and configures the SDAx and SCLx pins as the source of the serial port pins(3) 0 = Disables serial port and configures these pins as I/O port pins CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2C Slave mode: SCLx release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I2C Master mode: Unused in this mode SSPxM<3:0>: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCKx pin, SSx pin control enabled 0101 = SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = I2C Master mode, clock = FOSC / (4 * (SSPxADD+1))(4) 1001 = Reserved 1010 = SPI Master mode, clock = FOSC/(4 * (SSPxADD+1))(5) 1011 = I2C firmware controlled Master mode (Slave idle) 1100 = Reserved 1101 = Reserved 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1: 2: 3: 4: 5: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. When enabled, these pins must be properly configured as input or output. When enabled, the SDAx and SCLx pins must be configured as inputs. SSPxADD values of 0, 1 or 2 are not supported for I2CTM mode. SSPxADD value of 0 is not supported. Use SSPxM = 0000 instead.
bit 6
bit 5
bit 4
bit 3-0
Note
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REGISTER 24-3:
R/W-0/0 GCEN bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets HC = Cleared by hardware S = User set
SSPxCON2: SSPx CONTROL REGISTER 2
R-0/0 R/W-0/0 ACKDT R/S/HS-0/0 ACKEN R/S/HS-0/0 RCEN R/S/HS-0/0 PEN R/S/HS-0/0 RSEN R/W/HS-0/0 SEN bit 0
ACKSTAT
GCEN: General Call Enable bit (in I2C Slave mode only) 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR 0 = General call address disabled ACKSTAT: Acknowledge Status bit (in I2C mode only) 1 = Acknowledge was not received 0 = Acknowledge was received ACKDT: Acknowledge Data bit (in I2C mode only) In Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDAx and SCLx pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence idle RCEN: Receive Enable bit (in I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive idle PEN: Stop Condition Enable bit (in I2C Master mode only) SCKx Release Control: 1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Stop condition Idle RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle SEN: Start Condition Enabled bit (in I2C Master mode only) In Master mode: 1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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REGISTER 24-4:
R-0/0 ACKTIM bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCLx clock 0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCLx clock PCIE: Stop Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled(2) SCIE: Start Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled(2) BOEN: Buffer Overwrite Enable bit In SPI Slave mode:(1) 1 = SSPxBUF updates every time that a new data byte is shifted in ignoring the BF bit 0 = If new byte is received with BF bit of the SSPxSTAT register already set, SSPxOV bit of the SSPxCON1 register is set, and the buffer is not updated In I2C Master mode and SPI Master mode: This bit is ignored. In I2C Slave mode: 1 = SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the state of the SSPxOV bit only if the BF bit = 0. 0 = SSPxBUF is only updated when SSPxOV is clear SDAHT: SDAx Hold Time Selection bit (I2C mode only) 1 = Minimum of 300 ns hold time on SDAx after the falling edge of SCLx 0 = Minimum of 100 ns hold time on SDAx after the falling edge of SCLx SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) If on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the BCLxIF bit of the PIR2 register is set, and bus goes idle 1 = Enable slave bus collision interrupts 0 = Slave bus collision interrupts are disabled bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCLx for a matching received address byte; CKP bit of the SSPxCON1 register will be cleared and the SCLx will be held low. 0 = Address holding is disabled DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCLx for a received data byte; slave hardware clears the CKP bit of the SSPxCON1 register and SCLx is held low. 0 = Data holding is disabled For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPxOV is still set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF. This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
SSPxCON3: SSPx CONTROL REGISTER 3
R/W-0/0 SCIE R/W-0/0 BOEN R/W-0/0 SDAHT R/W-0/0 SBCDE R/W-0/0 AHEN R/W-0/0 DHEN bit 0 PCIE
R/W-0/0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 0
Note 1: 2: 3:
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REGISTER 24-5:
R/W-1/1 bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-1 W = Writable bit x = Bit is unknown `0' = Bit is cleared MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPxADD to detect I2C address match 0 = The received address bit n is not used to detect I2C address match MSK<0>: Mask bit for I2C Slave mode, 10-bit Address I2C Slave mode, 10-bit address (SSPxM<3:0> = 0111 or 1111): 1 = The received address bit 0 is compared to SSPxADD<0> to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match I2C Slave mode, 7-bit address, the bit is ignored U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
SSPxMSK: SSPx MASK REGISTER
R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 bit 0 MSK<7:0>
R/W-1/1
bit 0
REGISTER 24-6:
R/W-0/0 bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set Master mode: bit 7-0
SSPxADD: MSSPx ADDRESS AND BAUD RATE REGISTER (I2C MODE)
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 bit 0 ADD<7:0>
R/W-0/0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
ADD<7:0>: Baud Rate Clock Divider bits SCLx pin clock period = ((ADD<7:0> + 1) *4)/FOSC
10-Bit Slave mode -- Most Significant Address byte: bit 7-3 Not used: Unused for Most Significant Address byte. Bit state of this register is a "don't care". Bit pattern sent by master is fixed by I2C specification and must be equal to `11110'. However, those bits are compared by hardware and are not affected by the value in this register. ADD<2:1>: Two Most Significant bits of 10-bit address Not used: Unused in this mode. Bit state is a "don't care".
bit 2-1 bit 0
10-Bit Slave mode -- Least Significant Address byte: bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address
7-Bit Slave mode: bit 7-1 bit 0 ADD<7:1>: 7-bit address Not used: Unused in this mode. Bit state is a "don't care".
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25.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART)
The EUSART module includes the following capabilities: * * * * * * * * * * Full-duplex asynchronous transmit and receive Two-character input buffer One-character output buffer Programmable 8-bit or 9-bit character length Address detection in 9-bit mode Input buffer overrun error detection Received character framing error detection Half-duplex synchronous master Half-duplex synchronous slave Programmable clock polarity in synchronous modes * Sleep operation The EUSART module implements the following additional features, making it ideally suited for use in Local Interconnect Network (LIN) bus systems: * Automatic detection and calibration of the baud rate * Wake-up on Break reception * 13-bit Break character transmit Block diagrams of the EUSART transmitter and receiver are shown in Figure 25-1 and Figure 25-2.
The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. The EUSART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals and personal computers. Half-Duplex Synchronous mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device.
FIGURE 25-1:
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus TXIE TXIF LSb Interrupt
TXREG Register 8 MSb (8)
TX/CK pin Pin Buffer and Control
***
Transmit Shift Register (TSR)
0
TXEN Baud Rate Generator BRG16 +1 SPBRGH SPBRGL Multiplier SYNC BRGH BRG16 TRMT FOSC /n n x4 x16 x64 0 0 0 1X00 X110 X101 TX9D TX9 SPEN
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FIGURE 25-2: EUSART RECEIVE BLOCK DIAGRAM
SPEN CREN OERR RCIDL
RX/DT pin Pin Buffer and Control Baud Rate Generator BRG16 +1 SPBRGH SPBRGL Multiplier SYNC BRGH BRG16 x4 x16 x64 0 0 0 FERR 1X00 X110 X101 FOSC Data Recovery
MSb Stop (8) 7
RSR Register
LSb 0 START
***
RX9
1
/n
n FIFO
RX9D
RCREG Register 8
Data Bus RCIF RCIE Interrupt
The operation of the EUSART module is controlled through three registers: * Transmit Status and Control (TXSTA) * Receive Status and Control (RCSTA) * Baud Rate Control (BAUDCON) These registers are detailed in Register 25-1, Register 25-2 and Register 25-3, respectively. When the receiver or transmitter section is not enabled then the corresponding RX or TX pin may be used for general purpose input and output.
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25.1 EUSART Asynchronous Mode
25.1.1.2 Transmitting Data
The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a `1' data bit, and a VOL space state which represents a `0' data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the mark state. Each character transmission consists of one Start bit followed by eight or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data format is 8 bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See Table 25-5 for examples of baud rate configurations. The EUSART transmits and receives the LSb first. The EUSART's transmitter and receiver are functionally independent, but share the same data format and baud rate. Parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. A transmission is initiated by writing a character to the TXREG register. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREG is immediately transferred to the TSR register. If the TSR still contains all or part of a previous character, the new character data is held in the TXREG until the Stop bit of the previous character has been transmitted. The pending character in the TXREG is then transferred to the TSR in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits and Stop bit sequence commences immediately following the transfer of the data to the TSR from the TXREG.
25.1.1.3
Transmit Interrupt Flag
25.1.1
EUSART ASYNCHRONOUS TRANSMITTER
The TXIF interrupt flag bit of the PIR1 register is set whenever the EUSART transmitter is enabled and no character is being held for transmission in the TXREG. In other words, the TXIF bit is only clear when the TSR is busy with a character and a new character has been queued for transmission in the TXREG. The TXIF flag bit is not cleared immediately upon writing TXREG. TXIF becomes valid in the second instruction cycle following the write execution. Polling TXIF immediately following the TXREG write will return invalid results. The TXIF bit is read-only, it cannot be set or cleared by software. The TXIF interrupt can be enabled by setting the TXIE interrupt enable bit of the PIE1 register. However, the TXIF flag bit will be set whenever the TXREG is empty, regardless of the state of TXIE enable bit. To use interrupts when transmitting data, set the TXIE bit only when there is more data to send. Clear the TXIE interrupt enable bit upon writing the last character of the transmission to the TXREG.
The EUSART transmitter block diagram is shown in Figure 25-1. The heart of the transmitter is the serial Transmit Shift Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which is the TXREG register.
25.1.1.1
Enabling the Transmitter
The EUSART transmitter is enabled for asynchronous operations by configuring the following three control bits: * TXEN = 1 * SYNC = 0 * SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the TXEN bit of the TXSTA register enables the transmitter circuitry of the EUSART. Clearing the SYNC bit of the TXSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the EUSART and automatically configures the TX/CK I/O pin as an output. If the TX/CK pin is shared with an analog peripheral, the analog I/O function must be disabled by clearing the corresponding ANSEL bit. Note 1: The TXIF Transmitter Interrupt flag is set when the TXEN enable bit is set.
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25.1.1.4 TSR Status 25.1.1.6
1.
Asynchronous Transmission Set-up:
The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: The TSR register is not mapped in data memory, so it is not available to the user.
2. 3.
25.1.1.5
Transmitting 9-Bit Characters
4.
The EUSART supports 9-bit character transmissions. When the TX9 bit of the TXSTA register is set, the EUSART will shift 9 bits out for each character transmitted. The TX9D bit of the TXSTA register is the ninth, and Most Significant, data bit. When transmitting 9-bit data, the TX9D data bit must be written before writing the 8 Least Significant bits into the TXREG. All nine bits of data will be transferred to the TSR shift register immediately after the TXREG is written. A special 9-bit Address mode is available for use with multiple receivers. See Section 25.1.2.7 "Address Detection" for more information on the address mode.
5.
6. 7.
Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 25.3 "EUSART Baud Rate Generator (BRG)"). Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the 8 Least Significant data bits are an address when the receiver is set for address detection. Enable the transmission by setting the TXEN control bit. This will cause the TXIF interrupt bit to be set. If interrupts are desired, set the TXIE interrupt enable bit of the PIE1 register. An interrupt will occur immediately provided that the GIE and PEIE bits of the INTCON register are also set. If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. Load 8-bit data into the TXREG register. This will start the transmission.
FIGURE 25-3:
Write to TXREG BRG Output (Shift Clock) TX/CK pin TXIF bit (Transmit Buffer Reg. Empty Flag)
ASYNCHRONOUS TRANSMISSION
Word 1
Start bit 1 TCY
bit 0
bit 1 Word 1
bit 7/8
Stop bit
TRMT bit (Transmit Shift Reg. Empty Flag)
Word 1 Transmit Shift Reg.
FIGURE 25-4:
Write to TXREG BRG Output (Shift Clock) TX/CK pin TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag)
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Word 1 Word 2
Start bit 1 TCY
bit 0
bit 1 Word 1
bit 7/8
Stop bit
Start bit Word 2
bit 0
1 TCY Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg.
Note:
This timing diagram shows two consecutive transmissions.
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TABLE 25-1:
Name APFCON0 APFCON1 BAUDCON INTCON PIE1 PIR1 RCSTA SPBRGL SPBRGH TRISB TXREG TXSTA Legend: Note * 1: TRISB7 TRISB6 TRISB5
SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7 RXDTSEL -- ABDOVF GIE TMR1GIE TMR1GIF SPEN Bit 6 SDO1SEL -- RCIDL PEIE ADIE ADIF RX9 Bit 5 SS1SEL -- -- TMR0IE RCIE RCIF SREN Bit 4 P2BSEL(1) -- SCKP INTE TXIE TXIF CREN Bit 3 CCP2SEL(1) -- BRG16 IOCIE SSPIE SSPIF ADDEN Bit 2 P1DSEL -- -- TMR0IF CCP1IE CCP1IF FERR Bit 1 P1CSEL -- WUE INTF TMR2IE TMR2IF OERR Bit 0 CCP1SEL TXCKSEL ABDEN IOCIF TMR1IE TMR1IF RX9D Register on Page 122 122 298 101 102 105 297 299* 299* TRISB2 TRISB1 TRISB0 129 289* SYNC SENDB BRGH TRMT TX9D 296
BRG<7:0> BRG<15:8> TRISB4 TRISB3
EUSART Transmit Data Register CSRC TX9 TXEN -- = unimplemented location, read as `0'. Shaded cells are not used for Asynchronous Transmission. Page provides register information. PIC16F/LF1827 only.
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25.1.2 EUSART ASYNCHRONOUS RECEIVER 25.1.2.2 Receiving Data
The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 25-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate. When all 8 or 9 bits of the character have been shifted in, they are immediately transferred to a two character First-In-First-Out (FIFO) memory. The FIFO buffering allows reception of two complete characters and the start of a third character before software must start servicing the EUSART receiver. The FIFO and RSR registers are not directly accessible by software. Access to the received data is via the RCREG register. The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the Start bit. If the Start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. The bit is then sampled by a majority detect circuit and the resulting `0' or `1' is shifted into the RSR. This repeats until all data bits have been sampled and shifted into the RSR. One final bit time is measured and the level sampled. This is the Stop bit, which is always a `1'. If the data recovery circuit samples a `0' in the Stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. See Section 25.1.2.4 "Receive Framing Error" for more information on framing errors. Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the EUSART receive FIFO and the RCIF interrupt flag bit of the PIR1 register is set. The top character in the FIFO is transferred out of the FIFO by reading the RCREG register. Note: If the receive FIFO is overrun, no additional characters will be received until the overrun condition is cleared. See Section 25.1.2.5 "Receive Overrun Error" for more information on overrun errors.
25.1.2.1
Enabling the Receiver
The EUSART receiver is enabled for asynchronous operation by configuring the following three control bits: * CREN = 1 * SYNC = 0 * SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the CREN bit of the RCSTA register enables the receiver circuitry of the EUSART. Clearing the SYNC bit of the TXSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the EUSART. The programmer must set the corresponding TRIS bit to configure the RX/DT I/O pin as an input. Note 1: If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function.
25.1.2.3
Receive Interrupts
The RCIF interrupt flag bit of the PIR1 register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RCIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCIF interrupts are enabled by setting all of the following bits: * RCIE interrupt enable bit of the PIE1 register * PEIE peripheral interrupt enable bit of the INTCON register * GIE global interrupt enable bit of the INTCON register The RCIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits.
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25.1.2.4 Receive Framing Error 25.1.2.7 Address Detection
Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG. The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error (FERR = 1) does not preclude reception of additional characters. It is not necessary to clear the FERR bit. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error. The FERR bit can be forced clear by clearing the SPEN bit of the RCSTA register which resets the EUSART. Clearing the CREN bit of the RCSTA register does not affect the FERR bit. A framing error by itself does not generate an interrupt. Note: If all receive characters in the receive FIFO have framing errors, repeated reads of the RCREG will not clear the FERR bit. A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems. Address detection is enabled by setting the ADDEN bit of the RCSTA register. Address detection requires 9-bit character reception. When address detection is enabled, only characters with the ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RCIF interrupt bit. All other characters will be ignored. Upon receiving an address character, user software determines if the address matches its own. Upon address match, user software must disable address detection by clearing the ADDEN bit before the next Stop bit occurs. When user software detects the end of the message, determined by the message protocol used, software places the receiver back into the Address Detection mode by setting the ADDEN bit.
25.1.2.5
Receive Overrun Error
The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTA register or by resetting the EUSART by clearing the SPEN bit of the RCSTA register.
25.1.2.6
Receiving 9-bit Characters
The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the EUSART will shift 9 bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG.
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25.1.2.8
1.
Asynchronous Reception Set-up:
25.1.2.9
9-bit Address Detection Mode Set-up
Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 25.3 "EUSART Baud Rate Generator (BRG)"). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 5. If 9-bit reception is desired, set the RX9 bit. 6. Enable reception by setting the CREN bit. 7. The RCIF interrupt flag bit will be set when a character is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit was also set. 8. Read the RCSTA register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. 9. Get the received 8 Least Significant data bits from the receive buffer by reading the RCREG register. 10. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit.
This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 25.3 "EUSART Baud Rate Generator (BRG)"). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 5. Enable 9-bit reception by setting the RX9 bit. 6. Enable address detection by setting the ADDEN bit. 7. Enable reception by setting the CREN bit. 8. The RCIF interrupt flag bit will be set when a character with the ninth bit set is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit was also set. 9. Read the RCSTA register to get the error flags. The ninth data bit will always be set. 10. Get the received 8 Least Significant data bits from the receive buffer by reading the RCREG register. Software determines if this is the device's address. 11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 12. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts.
FIGURE 25-5:
RX/DT pin Rcv Shift Reg Rcv Buffer Reg. RCIDL Read Rcv Buffer Reg. RCREG RCIF (Interrupt Flag) OERR bit CREN
ASYNCHRONOUS RECEPTION
Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 bit 7/8 Stop bit Start bit bit 7/8 Stop bit
Word 1 RCREG
Word 2 RCREG
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.
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TABLE 25-2:
Name APFCON0 APFCON1 BAUDCON INTCON PIE1 PIR1 RCREG RCSTA SPBRGL SPBRGH TRISB TXSTA Legend: * Note 1: TRISB7 CSRC TRISB6 TX9 TRISB5 TXEN SPEN RX9 SREN
SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7 RXDTSEL -- ABDOVF GIE TMR1GIE TMR1GIF Bit 6 SDO1SEL -- RCIDL PEIE ADIE ADIF Bit 5 SS1SEL -- -- TMR0IE RCIE RCIF Bit 4 Bit 3 Bit 2 P1DSEL -- -- TMR0IF CCP1IE CCP1IF FERR Bit 1 P1CSEL -- WUE INTF TMR2IE TMR2IF OERR Bit 0 CCP1SEL TXCKSEL ABDEN IOCIF TMR1IE TMR1IF RX9D Register on Page 122 122 298 101 102 105 292* 297 299* 299* TRISB2 BRGH TRISB1 TRMT TRISB0 TX9D 129 296
P2BSEL(1) CCP2SEL(1) -- SCKP INTE TXIE TXIF CREN -- BRG16 IOCIE SSPIE SSPIF ADDEN
EUSART Receive Data Register BRG<7:0> BRG<15:8> TRISB4 SYNC TRISB3 SENDB
-- = unimplemented location, read as `0'. Shaded cells are not used for Asynchronous Reception. Page provides register information. PIC16F/LF1827 only.
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25.2 Clock Accuracy with Asynchronous Operation
The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source. See Section 6.2.2 "Internal Clock Sources" for more information. The other method adjusts the value in the Baud Rate Generator. This can be done automatically with the Auto-Baud Detect feature (see Section 25.3.1 "Auto-Baud Detect"). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency.
The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind.
REGISTER 25-1:
R/W-/0 CSRC bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0/0 TX9 R/W-0/0 TXEN(1) R/W-0/0 SYNC R/W-0/0 SENDB R/W-0/0 BRGH R-1/1 TRMT R/W-0/0 TX9D bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
CSRC: Clock Source Select bit Asynchronous mode: Don't care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don't care BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. SREN/CREN overrides TXEN in Sync mode.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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REGISTER 25-2:
R/W-0/0 SPEN bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode: Don't care Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave Don't care CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don't care FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1)
R/W-0/0 SREN R/W-0/0 CREN R/W-0/0 ADDEN R-0/0 FERR R-0/0 OERR R-x/x RX9D bit 0 RX9
R/W-0/0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 25-3:
R-0/0 ABDOVF bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don't care RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been received and the receiver is receiving Synchronous mode: Don't care Unimplemented: Read as `0' SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: 1 = Transmit inverted data to the TX/CK pin 0 = Transmit non-inverted data to the TX/CK pin Synchronous mode: 1 = Data is clocked on rising edge of the clock 0 = Data is clocked on falling edge of the clock BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used 0 = 8-bit Baud Rate Generator is used Unimplemented: Read as `0' WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE will automatically clear after RCIF is set. 0 = Receiver is operating normally Synchronous mode: Don't care ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don't care U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
BAUDCON: BAUD RATE CONTROL REGISTER
R-1/1 RCIDL U-0 -- R/W-0/0 SCKP R/W-0/0 BRG16 U-0 -- R/W-0/0 WUE R/W-0/0 ABDEN bit 0
bit 6
bit 5 bit 4
bit 3
bit 2 bit 1
bit 0
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25.3 EUSART Baud Rate Generator (BRG)
EXAMPLE 25-1: CALCULATING BAUD RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
FOSC Desired Baud Rate = ----------------------------------------------------------------------64 [SPBRGH:SPBRGL] + 1
The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCON register selects 16-bit mode. The SPBRGH, SPBRGL register pair determines the period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate period is determined by both the BRGH bit of the TXSTA register and the BRG16 bit of the BAUDCON register. In Synchronous mode, the BRGH bit is ignored. Table 25-3 contains the formulas for determining the baud rate. Example 25-1 provides a sample calculation for determining the baud rate and baud rate error. Typical baud rates and error values for various asynchronous modes have been computed for your convenience and are shown in Table 25-3. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the baud rate error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. Writing a new value to the SPBRGH, SPBRGL register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is Idle before changing the system clock.
Solving for SPBRGH:SPBRGL:
FOSC -------------------------------------------Desired Baud Rate X = --------------------------------------------- - 1 64 16000000 ----------------------9600 = ----------------------- - 1 64 = 25.042 = 25 16000000 Calculated Baud Rate = -------------------------64 25 + 1 = 9615 Calc. Baud Rate - Desired Baud Rate Error = ------------------------------------------------------------------------------------------Desired Baud Rate 9615 - 9600 = ---------------------------------- = 0.16% 9600
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TABLE 25-3:
SYNC 0 0 0 0 1 1 Legend:
BAUD RATE FORMULAS
BRG16 0 0 1 1 0 1 BRGH 0 1 0 1 x x BRG/EUSART Mode 8-bit/Asynchronous 8-bit/Asynchronous 16-bit/Asynchronous 16-bit/Asynchronous 8-bit/Synchronous 16-bit/Synchronous FOSC/[4 (n+1)] Baud Rate Formula FOSC/[64 (n+1)] FOSC/[16 (n+1)]
Configuration Bits
x = Don't care, n = value of SPBRGH, SPBRGL register pair
TABLE 25-4:
Name BAUDCON RCSTA SPBRGL SPBRGH TXSTA
SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Bit 7 ABDOVF SPEN Bit 6 RCIDL RX9 Bit 5 -- SREN Bit 4 SCKP CREN Bit 3 BRG16 ADDEN Bit 2 -- FERR Bit 1 WUE OERR Bit 0 ABDEN RX9D Register on Page 298 297 299* 299* BRGH TRMT TX9D 296
BRG<7:0> BRG<15:8> CSRC TX9 TXEN SYNC SENDB
Legend: -- = unimplemented location, read as `0'. Shaded cells are not used for the Baud Rate Generator. * Page provides register information.
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TABLE 25-5:
BAUD RATE
BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0 FOSC = 20.000 MHz Actual Rate -- 1221 2404 9470 10417 19.53k -- -- % Error -- 1.73 0.16 -1.36 0.00 1.73 -- -- SPBRG value (decimal) -- 255 129 32 29 15 -- -- FOSC = 18.432 MHz Actual Rate -- 1200 2400 9600 10286 19.20k 57.60k -- % Error -- 0.00 0.00 0.00 -1.26 0.00 0.00 -- SPBRG value (decimal) -- 239 119 29 27 14 7 -- FOSC = 11.0592 MHz Actual Rate -- 1200 2400 9600 10165 19.20k 57.60k -- % Error -- 0.00 0.00 0.00 -2.42 0.00 0.00 -- SPBRG value (decimal) -- 143 71 17 16 8 2 --
FOSC = 32.000 MHz Actual Rate -- -- 2404 9615 10417 19.23k 55.55k -- % Error -- -- 0.16 0.16 0.00 0.16 -3.55 -- SPBRG value (decimal) -- -- 207 51 47 25 3 --
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate -- 1202 2404 9615 10417 -- -- -- % Error -- 0.16 0.16 0.16 0.00 -- -- -- SPBRG value (decimal) -- 103 51 12 11 -- -- -- FOSC = 4.000 MHz Actual Rate 300 1202 2404 -- 10417 -- -- -- % Error 0.16 0.16 0.16 -- 0.00 -- -- -- SPBRG value (decimal) 207 51 25 -- 5 -- -- -- FOSC = 3.6864 MHz Actual Rate 300 1200 2400 9600 -- 19.20k 57.60k -- % Error 0.00 0.00 0.00 0.00 -- 0.00 0.00 -- SPBRG value (decimal) 191 47 23 5 -- 2 0 -- FOSC = 1.000 MHz Actual Rate 300 1202 -- -- -- -- -- -- % Error 0.16 0.16 -- -- -- -- -- -- SPBRG value (decimal) 51 12 -- -- -- -- -- --
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 32.000 MHz Actual Rate -- -- -- 9615 10417 19.23k 57.14k 117.64k % Error -- -- -- 0.16 0.00 0.16 -0.79 2.12 SPBRG value (decimal) -- -- -- 207 191 103 34 16 FOSC = 20.000 MHz Actual Rate -- -- -- 9615 10417 19.23k 56.82k 113.64k % Error -- -- -- 0.16 0.00 0.16 -1.36 -1.36 SPBRG value (decimal) -- -- -- 129 119 64 21 10 FOSC = 18.432 MHz Actual Rate -- -- -- 9600 10378 19.20k 57.60k 115.2k % Error -- -- -- 0.00 -0.37 0.00 0.00 0.00 SPBRG value (decimal) -- -- -- 119 110 59 19 9 FOSC = 11.0592 MHz Actual Rate -- -- -- 9600 10473 19.20k 57.60k 115.2k % Error -- -- -- 0.00 0.53 0.00 0.00 0.00 SPBRG value (decimal) -- -- -- 71 65 35 11 5
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
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TABLE 25-5:
BAUD RATE
BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 0 FOSC = 4.000 MHz Actual Rate -- 1202 2404 9615 10417 19.23k -- -- % Error -- 0.16 0.16 0.16 0.00 0.16 -- -- SPBRG value (decimal) -- 207 103 25 23 12 -- -- FOSC = 3.6864 MHz Actual Rate -- 1200 2400 9600 10473 19.2k 57.60k 115.2k % Error -- 0.00 0.00 0.00 0.53 0.00 0.00 0.00 SPBRG value (decimal) -- 191 95 23 21 11 3 1 FOSC = 1.000 MHz Actual Rate 300 1202 2404 -- 10417 -- -- -- % Error 0.16 0.16 0.16 -- 0.00 -- -- -- SPBRG value (decimal) 207 51 25 -- 5 -- -- --
FOSC = 8.000 MHz Actual Rate -- -- 2404 9615 10417 19231 55556 -- % Error -- -- 0.16 0.16 0.00 0.16 -3.55 -- SPBRG value (decimal) -- -- 207 51 47 25 8 --
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 32.000 MHz Actual Rate 300.0 1200 2401 9615 10417 19.23k 57.14k 117.6k % Error 0.00 -0.02 -0.04 0.16 0.00 0.16 -0.79 2.12 SPBRG value (decimal) 6666 3332 832 207 191 103 34 16 FOSC = 20.000 MHz Actual Rate 300.0 1200 2399 9615 10417 19.23k 56.818 113.636 % Error -0.01 -0.03 -0.03 0.16 0.00 0.16 -1.36 -1.36 SPBRG value (decimal) 4166 1041 520 129 119 64 21 10 FOSC = 18.432 MHz Actual Rate 300.0 1200 2400 9600 10378 19.20k 57.60k 115.2k % Error 0.00 0.00 0.00 0.00 -0.37 0.00 0.00 0.00 SPBRG value (decimal) 3839 959 479 119 110 59 19 9 FOSC = 11.0592 MHz Actual Rate 300.0 1200 2400 9600 10473 19.20k 57.60k 115.2k % Error 0.00 0.00 0.00 0.00 0.53 0.00 0.00 0.00 SPBRG value (decimal) 2303 575 287 71 65 35 11 5
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate 299.9 1199 2404 9615 10417 19.23k 55556 -- % Error -0.02 -0.08 0.16 0.16 0.00 0.16 -3.55 -- SPBRG value (decimal) 1666 416 207 51 47 25 8 -- FOSC = 4.000 MHz Actual Rate 300.1 1202 2404 9615 10417 19.23k -- -- % Error 0.04 0.16 0.16 0.16 0.00 0.16 -- -- SPBRG value (decimal) 832 207 103 25 23 12 -- -- FOSC = 3.6864 MHz Actual Rate 300.0 1200 2400 9600 10473 19.20k 57.60k 115.2k % Error 0.00 0.00 0.00 0.00 0.53 0.00 0.00 0.00 SPBRG value (decimal) 767 191 95 23 21 11 3 1 FOSC = 1.000 MHz Actual Rate 300.5 1202 2404 -- 10417 -- -- -- % Error 0.16 0.16 0.16 -- 0.00 -- -- -- SPBRG value (decimal) 207 51 25 -- 5 -- -- --
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
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TABLE 25-5:
BAUD RATE
BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 FOSC = 20.000 MHz Actual Rate 300.0 1200 2400 9597 10417 19.23k 57.47k 116.3k % Error 0.00 -0.01 0.02 -0.03 0.00 0.16 -0.22 0.94 SPBRG value (decimal) 16665 4166 2082 520 479 259 86 42 FOSC = 18.432 MHz Actual Rate 300.0 1200 2400 9600 10425 19.20k 57.60k 115.2k % Error 0.00 0.00 0.00 0.00 0.08 0.00 0.00 0.00 SPBRG value (decimal) 15359 3839 1919 479 441 239 79 39 FOSC = 11.0592 MHz Actual Rate 300.0 1200 2400 9600 10433 19.20k 57.60k 115.2k % Error 0.00 0.00 0.00 0.00 0.16 0.00 0.00 0.00 SPBRG value (decimal) 9215 2303 1151 287 264 143 47 23
FOSC = 32.000 MHz Actual Rate 300.0 1200 2400 9604 10417 19.18k 57.55k 115.9k % Error 0.00 0.00 0.01 0.04 0.00 -0.08 -0.08 0.64 SPBRG value (decimal) 26666 6666 3332 832 767 416 138 68
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate 300.0 1200 2401 9615 10417 19.23k 57.14k 117.6k % Error 0.00 -0.02 0.04 0.16 0 0.16 -0.79 2.12 SPBRG value (decimal) 6666 1666 832 207 191 103 34 16 FOSC = 4.000 MHz Actual Rate 300.0 1200 2398 9615 10417 19.23k 58.82k 111.1k % Error 0.01 0.04 0.08 0.16 0.00 0.16 2.12 -3.55 SPBRG value (decimal) 3332 832 416 103 95 51 16 8 FOSC = 3.6864 MHz Actual Rate 300.0 1200 2400 9600 10473 19.20k 57.60k 115.2k % Error 0.00 0.00 0.00 0.00 0.53 0.00 0.00 0.00 SPBRG value (decimal) 3071 767 383 95 87 47 15 7 FOSC = 1.000 MHz Actual Rate 300.1 1202 2404 9615 10417 19.23k -- -- % Error 0.04 0.16 0.16 0.16 0.00 0.16 -- -- SPBRG value (decimal) 832 207 103 25 23 12 -- --
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
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25.3.1 AUTO-BAUD DETECT
The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII "U") which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge. Setting the ABDEN bit of the BAUDCON register starts the auto-baud calibration sequence (Figure 25-6). While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of the receive line, after the Start bit, the SPBRG begins counting up using the BRG counter clock as shown in Table 25-6. The fifth rising edge will occur on the RX pin at the end of the eighth bit period. At that time, an accumulated value totaling the proper BRG period is left in the SPBRGH, SPBRGL register pair, the ABDEN bit is automatically cleared and the RCIF interrupt flag is set. The value in the RCREG needs to be read to clear the RCIF interrupt. RCREG content should be discarded. When calibrating for modes that do not use the SPBRGH register the user can verify that the SPBRGL register did not overflow by checking for 00h in the SPBRGH register. The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table 25-6. During ABD, both the SPBRGH and SPBRGL registers are used as a 16-bit counter, independent of the BRG16 bit setting. While calibrating the baud rate period, the SPBRGH and SPBRGL registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. Note 1: If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break character (see Section 25.3.3 "Auto-Wake-up on Break"). 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible. 3: During the auto-baud process, the auto-baud counter starts counting at 1. Upon completion of the auto-baud sequence, to achieve maximum accuracy, subtract 1 from the SPBRGH:SPBRGL register pair.
TABLE 25-6:
BRG16 0 0 1 1 Note: BRGH 0 1 0 1
BRG COUNTER CLOCK RATES
BRG Base Clock FOSC/64 FOSC/16 FOSC/16 FOSC/4 BRG ABD Clock FOSC/512 FOSC/128 FOSC/128 FOSC/32
During the ABD sequence, SPBRGL and SPBRGH registers are both used as a 16-bit counter, independent of BRG16 setting.
FIGURE 25-6:
BRG Value RX pin BRG Clock Set by User ABDEN bit RCIDL RCIF bit (Interrupt) Read RCREG SPBRGL SPBRGH Note 1:
AUTOMATIC BAUD RATE CALIBRATION
XXXXh 0000h Start Edge #1 bit 1 bit 0 Edge #2 bit 3 bit 2 Edge #3 bit 5 bit 4 Edge #4 bit 7 bit 6 001Ch Edge #5 Stop bit
Auto Cleared
XXh XXh The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
1Ch 00h
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25.3.2 AUTO-BAUD OVERFLOW 25.3.3.1 Special Considerations
During the course of automatic baud detection, the ABDOVF bit of the BAUDCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRGL register pair. After the ABDOVF has been set, the counter continues to count until the fifth rising edge is detected on the RX pin. Upon detecting the fifth RX edge, the hardware will set the RCIF interrupt flag and clear the ABDEN bit of the BAUDCON register. The RCIF flag can be subsequently cleared by reading the RCREG register. The ABDOVF flag of the BAUDCON register can be cleared by software directly. To terminate the auto-baud process before the RCIF flag is set, clear the ABDEN bit then clear the ABDOVF bit of the BAUDCON register. The ABDOVF bit will remain set if the ABDEN bit is not cleared first. Break Character To avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros. When the wake-up is enabled the function works independent of the low time on the data stream. If the WUE bit is set and a valid non-zero character is received, the low time from the Start bit to the first rising edge will be interpreted as the wake-up event. The remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. Therefore, the initial character in the transmission must be all `0's. This must be 10 or more bit times, 13-bit times recommended for LIN bus, or any number of bit times for standard RS-232 devices. Oscillator Start-up Time Oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., LP, XT or HS/PLL mode). The Sync Break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. WUE Bit The wake-up event causes a receive interrupt by setting the RCIF bit. The WUE bit is cleared in hardware by a rising edge on RX/DT. The interrupt condition is then cleared in software by reading the RCREG register and discarding its contents. To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode.
25.3.3
AUTO-WAKE-UP ON BREAK
During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RX/DT line. This feature is available only in Asynchronous mode. The Auto-Wake-up feature is enabled by setting the WUE bit of the BAUDCON register. Once set, the normal receive sequence on RX/DT is disabled, and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a wake-up signal character for the LIN protocol.) The EUSART module generates an RCIF interrupt coincident with the wake-up event. The interrupt is generated synchronously to the Q clocks in normal CPU operating modes (Figure 25-7), and asynchronously if the device is in Sleep mode (Figure 25-8). The interrupt condition is cleared by reading the RCREG register. The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character.
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FIGURE 25-7:
OSC1 WUE bit RX/DT Line RCIF Note 1: The EUSART remains in Idle while the WUE bit is set.
AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Bit set by user Auto Cleared
Cleared due to User Read of RCREG
FIGURE 25-8:
OSC1
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Auto Cleared
Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Bit Set by User WUE bit RX/DT Line RCIF Sleep Command Executed Note 1: 2:
Note 1 Sleep Ends Cleared due to User Read of RCREG
If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set.
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25.3.4 BREAK CHARACTER SEQUENCE 25.3.5 RECEIVING A BREAK CHARACTER
The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 `0' bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXSTA register. The Break character transmission is then initiated by a write to the TXREG. The value of data written to TXREG will be ignored and all `0's will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). The TRMT bit of the TXSTA register indicates when the transmit operation is active or Idle, just as it does during normal transmission. See Figure 25-9 for the timing of the Break character sequence. The Enhanced EUSART module can receive a Break character in two ways. The first method to detect a Break character uses the FERR bit of the RCSTA register and the Received data as indicated by RCREG. The Baud Rate Generator is assumed to have been initialized to the expected baud rate. A Break character has been received when; * RCIF bit is set * FERR bit is set * RCREG = 00h The second method uses the Auto-Wake-up feature described in Section 25.3.3 "Auto-Wake-up on Break". By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an RCIF interrupt, and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Detect feature. For both methods, the user can set the ABDEN bit of the BAUDCON register before placing the EUSART in Sleep mode.
25.3.4.1
Break and Sync Transmit Sequence
The following sequence will start a message frame header made up of a Break, followed by an auto-baud Sync byte. This sequence is typical of a LIN bus master. 1. 2. 3. 4. 5. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to enable the Break sequence. Load the TXREG with a dummy character to initiate transmission (the value is ignored). Write `55h' to TXREG to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted.
When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG.
FIGURE 25-9:
Write to TXREG BRG Output (Shift Clock) TX (pin)
SEND BREAK CHARACTER SEQUENCE
Dummy Write
Start bit
bit 0
bit 1 Break
bit 11
Stop bit
TXIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB (send Break control bit)
SENDB Sampled Here
Auto Cleared
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25.4 EUSART Synchronous Mode
Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. The EUSART can operate as either a master or slave device. Start and Stop bits are not used in synchronous transmissions. Clearing the SCKP bit sets the Idle state as low. When the SCKP bit is cleared, the data changes on the rising edge of each clock.
25.4.1.3
Synchronous Master Transmission
Data is transferred out of the device on the RX/DT pin. The RX/DT and TX/CK pin output drivers are automatically enabled when the EUSART is configured for synchronous master transmit operation. A transmission is initiated by writing a character to the TXREG register. If the TSR still contains all or part of a previous character the new character data is held in the TXREG until the last bit of the previous character has been transmitted. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREG is immediately transferred to the TSR. The transmission of the character commences immediately following the transfer of the data to the TSR from the TXREG. Each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge. Note: The TSR register is not mapped in data memory, so it is not available to the user.
25.4.1
SYNCHRONOUS MASTER MODE
The following bits are used to configure the EUSART for Synchronous Master operation: * * * * * SYNC = 1 CSRC = 1 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1
25.4.1.4
1.
Synchronous Master Transmission Set-up:
Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Setting the CSRC bit of the TXSTA register configures the device as a master. Clearing the SREN and CREN bits of the RCSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the EUSART.
2. 3. 4. 5. 6.
25.4.1.1
Master Clock
7. 8.
Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a master transmits the clock on the TX/CK line. The TX/CK pin output driver is automatically enabled when the EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits.
Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 25.3 "EUSART Baud Rate Generator (BRG)"). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Disable Receive mode by clearing bits SREN and CREN. Enable Transmit mode by setting the TXEN bit. If 9-bit transmission is desired, set the TX9 bit. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit. Start transmission by loading data to the TXREG register.
25.4.1.2
Clock Polarity
A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the SCKP bit of the BAUDCON register. Setting the SCKP bit sets the clock Idle state as high. When the SCKP bit is set, the data changes on the falling edge of each clock.
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FIGURE 25-10: SYNCHRONOUS TRANSMISSION
RX/DT pin TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg TXIF bit (Interrupt Flag) TRMT bit Write Word 1
bit 0
bit 1 Word 1
bit 2
bit 7
bit 0
bit 1 Word 2
bit 7
Write Word 2
TXEN bit Note:
`1' Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.
`1'
FIGURE 25-11:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7
TX/CK pin Write to TXREG reg
TXIF bit
TRMT bit
TXEN bit
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TABLE 25-7:
Name APFCON0 APFCON1 BAUDCON INTCON PIE1 PIR1 RCSTA SPBRGL SPBRGH TRISB TXREG TXSTA Legend: * Note 1: CSRC TX9 TRISB7 TRISB6 TRISB5 TXEN
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Bit 7 RXDTSEL -- ABDOVF GIE TMR1GIE TMR1GIF SPEN Bit 6 SDO1SEL -- RCIDL PEIE ADIE ADIF RX9 Bit 5 SS1SEL -- -- TMR0IE RCIE RCIF SREN Bit 4 Bit 3 Bit 2 P1DSEL -- -- TMR0IF CCP1IE CCP1IF FERR Bit 1 P1CSEL -- WUE INTF TMR2IE TMR2IF OERR Bit 0 CCP1SEL TXCKSEL ABDEN IOCIF TMR1IE TMR1IF RX9D Register on Page 122 122 298 101 102 105 297 299* 299* TRISB2 BRGH TRISB1 TRMT TRISB0 TX9D 129 289* 296
P2BSEL(1) CCP2SEL(1) -- SCKP INTE TXIE TXIF CREN -- BRG16 IOCIE SSPIE SSPIF ADDEN
BRG<7:0> BRG<15:8> TRISB4 SYNC TRISB3 SENDB EUSART Transmit Data Register -- = unimplemented location, read as `0'. Shaded cells are not used for Synchronous Master Transmission. Page provides register information. PIC16F/LF1827 only.
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25.4.1.5 Synchronous Master Reception
Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register). When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a single character. The SREN bit is automatically cleared at the completion of one character. When CREN is set, clocks are continuously generated until CREN is cleared. If CREN is cleared in the middle of a character the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then SREN is cleared at the completion of the first character and CREN takes precedence. To initiate reception, set either SREN or CREN. Data is sampled at the RX/DT pin on the trailing edge of the TX/CK clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is received into the RSR, the RCIF bit is set and the character is automatically transferred to the two character receive FIFO. The Least Significant eight bits of the top character in the receive FIFO are available in RCREG. The RCIF bit remains set as long as there are unread characters in the receive FIFO. Note: If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function. will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCREG. If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART.
25.4.1.8
Receiving 9-bit Characters
The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the EUSART will shift 9-bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth, and Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG.
25.4.1.9
1.
Synchronous Master Reception Set-up:
25.4.1.6
Slave Clock
Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a slave receives the clock on the TX/CK line. The TX/CK pin output driver is automatically disabled when the device is configured for synchronous slave transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One data bit is transferred for each clock cycle. Only as many clock cycles should be received as there are data bits. Note: If the device is configured as a slave and the TX/CK function is on an analog pin, the corresponding ANSEL bit must be cleared.
Initialize the SPBRGH, SPBRGL register pair for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 4. Ensure bits CREN and SREN are clear. 5. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 6. If 9-bit reception is desired, set bit RX9. 7. Start reception by setting the SREN bit or for continuous reception, set the CREN bit. 8. Interrupt flag bit RCIF will be set when reception of a character is complete. An interrupt will be generated if the enable bit RCIE was set. 9. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 10. Read the 8-bit received data by reading the RCREG register. 11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART.
25.4.1.7
Receive Overrun Error
The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCREG is read to access the FIFO. When this happens the OERR bit of the RCSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters
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FIGURE 25-12:
RX/DT pin TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit `0' RCIF bit (Interrupt) Read RCREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. `0'
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TABLE 25-8:
Name APFCON0 APFCON1 BAUDCON INTCON PIE1 PIR1 RCREG RCSTA SPBRGL SPBRGH TRISB TXSTA Legend: * Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 7 RXDTSEL
--
Bit 6 SDO1SEL
--
Bit 5 SS1SEL
--
Bit 4
Bit 3
Bit 2 P1DSEL
--
Bit 1 P1CSEL
--
Bit 0 CCP1SEL TXCKSEL ABDEN IOCIF TMR1IE TMR1IF RX9D
Register on Page 122 122 298 101 102 105 292* 297 299* 299*
P2BSEL(1) CCP2SEL(1)
-- --
ABDOVF GIE TMR1GIE TMR1GIF SPEN
RCIDL PEIE ADIE ADIF RX9
-- TMR0IE RCIE RCIF SREN
SCKP INTE TXIE TXIF CREN
BRG16 IOCIE SSPIE SSPIF ADDEN
-- TMR0IF CCP1IE CCP1IF FERR
WUE INTF TMR2IE TMR2IF OERR
EUSART Receive Data Register BRG<7:0> BRG<15:8> TRISB7 CSRC TRISB6 TX9 TRISB5 TXEN TRISB4 SYNC TRISB3 SENDB TRISB2 BRGH TRISB1 TRMT TRISB0 TX9D
129 296
-- = unimplemented location, read as `0'. Shaded cells are not used for Synchronous Master Reception. Page provides register information. PIC16F/LF1827 only.
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25.4.2 SYNCHRONOUS SLAVE MODE
The following bits are used to configure the EUSART for Synchronous slave operation: * * * * * SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: 1. 2. 3. 4. The first character will immediately transfer to the TSR register and transmit. The second word will remain in TXREG register. The TXIF bit will not be set. After the first character has been shifted out of TSR, the TXREG register will transfer the second character to the TSR and the TXIF bit will now be set. If the PEIE and TXIE bits are set, the interrupt will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine.
Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTA register configures the device as a slave. Clearing the SREN and CREN bits of the RCSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the EUSART.
5.
25.4.2.2
1. 2. 3. 4.
Synchronous Slave Transmission Set-up:
25.4.2.1
EUSART Synchronous Slave Transmit
The operation of the Synchronous Master and Slave modes are identical (see Section 25.4.1.3 "Synchronous Master Transmission"), except in the case of the Sleep mode.
5. 6. 7. 8.
Set the SYNC and SPEN bits and clear the CSRC bit. Clear the ANSEL bit for the CK pin (if applicable). Clear the CREN and SREN bits. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is desired, set the TX9 bit. Enable transmission by setting the TXEN bit. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. Start transmission by writing the Least Significant 8 bits to the TXREG register.
TABLE 25-9:
Name APFCON0 APFCON1 BAUDCON INTCON PIE1 PIR1 RCSTA TRISB TXREG TXSTA Legend: * Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Bit 7 RXDTSEL -- ABDOVF GIE TMR1GIE TMR1GIF SPEN TRISB7 CSRC Bit 6 SDO1SEL -- RCIDL PEIE ADIE ADIF RX9 TRISB6 TX9 Bit 5 SS1SEL -- -- TMR0IE RCIE RCIF SREN TRISB5 TXEN Bit 4 Bit 3 Bit 2 P1DSEL -- -- TMR0IF CCP1IE CCP1IF FERR TRISB2 BRGH Bit 1 P1CSEL -- WUE INTF TMR2IE TMR2IF OERR TRISB1 TRMT Bit 0 CCP1SEL TXCKSEL ABDEN IOCIF TMR1IE TMR1IF RX9D TRISB0 TX9D Register on Page 122 122 298 101 102 105 297 129 289* 296
P2BSEL(1) CCP2SEL(1) -- SCKP INTE TXIE TXIF CREN TRISB4 SYNC -- BRG16 IOCIE SSPIE SSPIF ADDEN TRISB3 SENDB
EUSART Transmit Data Register
-- = unimplemented location, read as `0'. Shaded cells are not used for Synchronous Slave Transmission. Page provides register information. PIC16F/LF1827 only.
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25.4.2.3 EUSART Synchronous Slave Reception 25.4.2.4
1. 2. 3.
Synchronous Slave Reception Set-up:
The operation of the Synchronous Master and Slave modes is identical (Section 25.4.1.5 "Synchronous Master Reception"), with the following exceptions: * Sleep * CREN bit is always set, therefore the receiver is never Idle * SREN bit, which is a "don't care" in Slave mode A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCREG register. If the RCIE enable bit is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will branch to the interrupt vector.
4. 5. 6.
7.
8. 9.
Set the SYNC and SPEN bits and clear the CSRC bit. Clear the ANSEL bit for both the CK and DT pins (if applicable). If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set the RX9 bit. Set the CREN bit to enable reception. The RCIF bit will be set when reception is complete. An interrupt will be generated if the RCIE bit was set. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCSTA register. Retrieve the 8 Least Significant bits from the receive FIFO by reading the RCREG register. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART.
TABLE 25-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name APFCON0 APFCON1 BAUDCON INTCON PIE1 PIR1 RCREG RCSTA TRISB TXSTA Legend: * Note 1: SPEN TRISB7 CSRC RX9 TRISB6 TX9 SREN TRISB5 TXEN Bit 7 RXDTSEL -- ABDOVF GIE TMR1GIE TMR1GIF Bit 6 SDO1SEL -- RCIDL PEIE ADIE ADIF Bit 5 SS1SEL -- -- TMR0IE RCIE RCIF Bit 4 Bit 3 Bit 2 P1DSEL -- -- TMR0IF CCP1IE CCP1IF Bit 1 P1CSEL -- WUE INTF TMR2IE TMR2IF Bit 0 CCP1SEL TXCKSEL ABDEN IOCIF TMR1IE TMR1IF Register on Page 122 122 298 101 102 105 292* FERR TRISB2 BRGH OERR TRISB1 TRMT RX9D TRISB0 TX9D 297 129 296
P2BSEL(1) CCP2SEL(1) -- SCKP INTE TXIE TXIF -- BRG16 IOCIE SSPIE SSPIF
EUSART Receive Data Register CREN TRISB4 SYNC ADDEN TRISB3 SENDB
-- = unimplemented location, read as `0'. Shaded cells are not used for Synchronous Slave Reception. Page provides register information. PIC16F/LF1827 only.
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25.5 EUSART Operation During Sleep
25.5.2
The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers.
SYNCHRONOUS TRANSMIT DURING SLEEP
To transmit during Sleep, all the following conditions must be met before entering Sleep mode: * RCSTA and TXSTA Control registers must be configured for Synchronous Slave Transmission (see Section 25.4.2.2 "Synchronous Slave Transmission Set-up:"). * The TXIF interrupt flag must be cleared by writing the output data to the TXREG, thereby filling the TSR and transmit buffer. * If interrupts are desired, set the TXIE bit of the PIE1 register and the PEIE bit of the INTCON register. * Interrupt enable bits TXIE of the PIE1 register and PEIE of the INTCON register must set. Upon entering Sleep mode, the device will be ready to accept clocks on TX/CK pin and transmit data on the RX/DT pin. When the data word in the TSR has been completely clocked out by the external device, the pending byte in the TXREG will transfer to the TSR and the TXIF flag will be set. Thereby, waking the processor from Sleep. At this point, the TXREG is available to accept another character for transmission, which will clear the TXIF flag. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit is also set then the Interrupt Service Routine at address 0004h will be called.
25.5.1
SYNCHRONOUS RECEIVE DURING SLEEP
To receive during Sleep, all the following conditions must be met before entering Sleep mode: * RCSTA and TXSTA Control registers must be configured for Synchronous Slave Reception (see Section 25.4.2.4 "Synchronous Slave Reception Set-up:"). * If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. * The RCIF interrupt flag must be cleared by reading RCREG to unload any pending characters in the receive buffer. Upon entering Sleep mode, the device will be ready to accept data and clocks on the RX/DT and TX/CK pins, respectively. When the data word has been completely clocked in by the external device, the RCIF interrupt flag bit of the PIR1 register will be set. Thereby, waking the processor from Sleep. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the GIE global interrupt enable bit of the INTCON register is also set, then the Interrupt Service Routine at address 004h will be called.
25.5.3
ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function registers, APFCON0 and APFCON1. To determine which pins can be moved and what their default locations are upon a Reset, see Section 12.1 "Alternate Pin Function" for more information.
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NOTES:
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26.0 CAPACITIVE SENSING MODULE
The capacitive sensing module allows for an interaction with an end user without a mechanical interface. In a typical application, the capacitive sensing module is attached to a pad on a Printed Circuit Board (PCB), which is electrically isolated from the end user. When the end user places their finger over the PCB pad, a capacitive load is added, causing a frequency shift in the capacitive sensing module. The capacitive sensing module requires software and at least one timer resource to determine the change in frequency. Key features of this module include: * * * * * Analog MUX for monitoring multiple inputs Capacitive sensing oscillator Multiple timer resources Software control Operation during Sleep
FIGURE 26-1:
CAPACITIVE SENSING BLOCK DIAGRAM
Timer0 Module TMR0CS FOSC/4 0 1 0 1 TMR0 Overflow Set TMR0IF
T0XCS T0CKI CPSCH<3:0> CPSON(1) CPS0 CPS1 CPS2 CPS3 CPS4 CPS5 CPS6 CPS7 CPS8 CPS9 CPS10 CPS11 SYNCC1OUT SYNCC2OUT CPSON Capacitive Sensing Oscillator CPSOSC T1CS<1:0> FOSC CPSCLK CPSOUT FOSC/4 T1OSC/ T1CKI T1GSEL<1:0> T1G
Timer1 Module
EN
TMR1H:TMR1L
CPSRNG<1:0>
Timer1 Gate Control Logic
Note 1:
If CPSON = 0, disabling capacitive sensing, no channel is selected.
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26.1 Analog MUX
26.4.1 TIMER0
The capacitive sensing module can monitor up to 12 inputs. The capacitive sensing inputs are defined as CPS<11:0>. To determine if a frequency change has occurred the user must: * Select the appropriate CPS pin by setting the CPSCH<3:0> bits of the CPSCON1 register * Set the corresponding ANSEL bit * Set the corresponding TRIS bit * Run the software algorithm Selection of the CPSx pin while the module is enabled will cause the capacitive sensing oscillator to be on the CPSx pin. Failure to set the corresponding ANSEL and TRIS bits can cause the capacitive sensing oscillator to stop, leading to false frequency readings. To select Timer0 as the timer resource for the capacitive sensing module: * Set the T0XCS bit of the CPSCON0 register * Clear the TMR0CS bit of the OPTION register When Timer0 is chosen as the timer resource, the capacitive sensing oscillator will be the clock source for Timer0. Refer to Section 19.0 "Timer0 Module" for additional information.
26.4.2
TIMER1
26.2
Capacitive Sensing Oscillator
The capacitive sensing oscillator consists of a constant current source and a constant current sink, to produce a triangle waveform. The CPSOUT bit of the CPSCON0 register shows the status of the capacitive sensing oscillator, whether it is a sinking or sourcing current. The oscillator is designed to drive a capacitive load (single PCB pad) and at the same time, be a clock source to either Timer0 or Timer1. The oscillator has three different current settings as defined by CPSRNG<1:0> of the CPSCON0 register. The different current settings for the oscillator serve two purposes: * Maximize the number of counts in a timer for a fixed time base * Maximize the count differential in the timer during a change in frequency
To select Timer1 as the timer resource for the capacitive sensing module, set the TMR1CS<1:0> of the T1CON register to `11'. When Timer1 is chosen as the timer resource, the capacitive sensing oscillator will be the clock source for Timer1. Because the Timer1 module has a gate control, developing a time base for the frequency measurement can be simplified by using the Timer0 overflow flag. It is recommend that the Timer0 overflow flag, in conjunction with the Toggle mode of the Timer1 Gate, be used to develop the fixed time base required by the software portion of the capacitive sensing module. Refer to Section 20.6.3 "Timer1 Gate Toggle Mode" for additional information.
TABLE 26-1:
TMR1ON 0 0 1 1
TIMER1 ENABLE FUNCTION
TMR1GE 0 1 0 1 Timer1 Operation Off Off On Count Enabled by input
26.3
Timer resources
To measure the change in frequency of the capacitive sensing oscillator, a fixed time base is required. For the period of the fixed time base, the capacitive sensing oscillator is used to clock either Timer0 or Timer1. The frequency of the capacitive sensing oscillator is equal to the number of counts in the timer divided by the period of the fixed time base.
26.4
Fixed Time Base
To measure the frequency of the capacitive sensing oscillator, a fixed time base is required. Any timer resource or software loop can be used to establish the fixed time base. It is up to the end user to determine the method in which the fixed time base is generated. Note: The fixed time base can not be generated by the timer resource that the capacitive sensing oscillator is clocking.
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26.5 Software Control
26.5.3 FREQUENCY THRESHOLD
The software portion of the capacitive sensing module is required to determine the change in frequency of the capacitive sensing oscillator. This is accomplished by the following: * Setting a fixed time base to acquire counts on Timer0 or Timer1 * Establishing the nominal frequency for the capacitive sensing oscillator * Establishing the reduced frequency for the capacitive sensing oscillator due to an additional capacitive load * Set the frequency threshold The frequency threshold should be placed midway between the value of nominal frequency and the reduced frequency of the capacitive sensing oscillator. Refer to Application Note AN1103, "Software Handling for Capacitive Sensing" (DS01103) for more detailed information on the software required for capacitive sensing module. Note: For more information on general capacitive sensing refer to Application Notes: * AN1101, "Introduction to Capacitive Sensing" (DS01101) * AN1102, "Layout and Physical Design Guidelines for Capacitive Sensing" (DS01102)
26.5.1
NOMINAL FREQUENCY (NO CAPACITIVE LOAD)
To determine the nominal frequency of the capacitive sensing oscillator: * Remove any extra capacitive load on the selected CPSx pin * At the start of the fixed time base, clear the timer resource * At the end of the fixed time base save the value in the timer resource The value of the timer resource is the number of oscillations of the capacitive sensing oscillator for the given time base. The frequency of the capacitive sensing oscillator is equal to the number of counts on in the timer divided by the period of the fixed time base.
26.6
Operation during Sleep
The capacitive sensing oscillator will continue to run as long as the module is enabled, independent of the part being in Sleep. In order for the software to determine if a frequency change has occurred, the part must be awake. However, the part does not have to be awake when the timer resource is acquiring counts. Note: Timer0 does not operate when in Sleep, and therefore cannot be used for capacitive sense measurements in Sleep.
26.5.2
REDUCED FREQUENCY (ADDITIONAL CAPACITIVE LOAD)
The extra capacitive load will cause the frequency of the capacitive sensing oscillator to decrease. To determine the reduced frequency of the capacitive sensing oscillator: * Add a typical capacitive load on the selected CPSx pin * Use the same fixed time base as the nominal frequency measurement * At the start of the fixed time base, clear the timer resource * At the end of the fixed time base save the value in the timer resource The value of the timer resource is the number of oscillations of the capacitive sensing oscillator with an additional capacitive load. The frequency of the capacitive sensing oscillator is equal to the number of counts on in the timer divided by the period of the fixed time base. This frequency should be less than the value obtained during the nominal frequency measurement.
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REGISTER 26-1:
R/W-0/0 CPSON bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared CPSON: Capacitive Sensing Module Enable bit 1 = Capacitive sensing module is enabled 0 = Capacitive sensing module is disabled Unimplemented: Read as `0' CPSRNG<1:0>: Capacitive Sensing Oscillator Range bits 00 = Oscillator is off 01 = Oscillator is in low range. Charge/discharge current is nominally 0.1 A. 10 = Oscillator is in medium range. Charge/discharge current is nominally 1.2 A. 11 = Oscillator is in high range. Charge/discharge current is nominally 18 A. CPSOUT: Capacitive Sensing Oscillator Status bit 1 = Oscillator is sourcing current (Current flowing out the pin) 0 = Oscillator is sinking current (Current flowing into the pin) T0XCS: Timer0 External Clock Source Select bit If TMR0CS = 1 The T0XCS bit controls which clock external to the core/Timer0 module supplies Timer0: 1 = Timer0 clock source is the capacitive sensing oscillator 0 = Timer0 clock source is the T0CKI pin If TMR0CS = 0 Timer0 clock source is controlled by the core/Timer0 module and is FOSC/4 U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
CPSCON0: CAPACITIVE SENSING CONTROL REGISTER 0
U-0 -- U-0 -- U-0 -- R/W-0/0 CPSRNG1 R/W-0/0 CPSRNG0 R-0/0 CPSOUT R/W-0/0 T0XCS bit 0
bit 6-4 bit 3-2
bit 1
bit 0
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REGISTER 26-2:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-4 bit 3-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0' CPSCH<3:0>: Capacitive Sensing Channel Select bits If CPSON = 0: These bits are ignored. No channel is selected. If CPSON = 1: 0000 = channel 0, (CPS0) 0001 = channel 1, (CPS1) 0010 = channel 2, (CPS2) 0011 = channel 3, (CPS3) 0100 = channel 4, (CPS4) 0101 = channel 5, (CPS5) 0110 = channel 6, (CPS6) 0111 = channel 7, (CPS7) 1000 = channel 8, (CPS8) 1001 = channel 9, (CPS9) 1010 = channel 10, (CPS10) 1011 = channel 11, (CPS11) 1100 = Reserved. Do not use. 1101 = Reserved. Do not use. 1110 = Reserved. Do not use. 1111 = Reserved. Do not use. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1
U-0 -- U-0 -- U-0 -- R/W-0/0 CPSCH3 R/W-0/0 CPSCH2 R/W-0/0 CPSCH1 R/W-0/0 CPSCH0 bit 0
TABLE 26-2:
Name ANSELA ANSELB CPSCON0 CPSCON1 INTCON OPTION_REG PIE1 PIR1 T1CON TxCON TRISA TRISB
SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING
Bit 7 -- ANSB7 CPSON -- GIE WPUEN TMR1GIE TMR1GIF TMR1CS1 -- TRISA7 TRISB7 Bit 6 -- ANSB6 -- -- PEIE INTEDG ADIE ADIF TMR1CS0 TRISA6 TRISB6 Bit 5 -- ANSB5 -- -- TMR0IE TMR0CS RCIE RCIF T1CKPS1 TRISA5 TRISB5 Bit 4 ANSA4 ANSB4 -- -- INTE TMR0SE TXIE TXIF T1CKPS0 TRISA4 TRISB4 Bit 3 ANSA3 ANSB3 CPSCH3 IOCIE PSA SSP1IE SSP1IF T1OSCEN TRISA3 TRISB3 Bit 2 ANSA2 ANSB2 CPSCH2 TMR0IF PS2 CCP1IE CCP1IF T1SYNC TMRxON TRISA2 TRISB2 Bit 1 ANSA1 ANSB1 CPSOUT CPSCH1 INTF PS1 TMR2IE TMR2IF -- TxCKPS1 TRISA1 TRISB1 Bit 0 ANSA0 -- T0XCS CPSCH0 IOCIF PS0 TMR1IE TMR1IF TMR1ON TxCKPS0 TRISA0 TRISB0 Register on Page 125 130 320 321 91 177 92 96 187 193 124 129
CPSRNG1 CPSRNG0
TxOUTPS3 TxOUTPS2 TxOUTPS1 TxOUTPS0
Legend: -- = Unimplemented locations, read as `0'. Shaded cells are not used by the capacitive sensing module.
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27.0 IN-CIRCUIT SERIAL PROGRAMMINGTM (ICSPTM)
ICSPTM programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSPTM programming: * ICSPCLK * ICSPDAT * MCLR/VPP * VDD * VSS In Program/Verify mode the Program Memory, User IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ICSPCLK pin is the clock input. For more information on ICSPTM refer to the "PIC16193X/PIC16LF193X Memory Programming Specification" (DS41360A).
27.1
High-Voltage Programming Entry Mode
The device is placed into High-Voltage Programming Entry mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP to VIHH. Some programmers produce VPP greater than VIHH (9.0V), an external circuit is required to limit the VPP voltage. See Figure 27-1 for example circuit.
FIGURE 27-1:
VPP LIMITER EXAMPLE CIRCUIT
RJ11-6PIN VPP VDD VSS ICSP_DATA ICSP_CLOCK NC RJ11-6PIN (R) 1 2 3 4 5 6 6 5 4 3 2 1
To MPLAB ICD 2
R1 270 Ohm LM431BCMX 1 2A K 3 A U1 6A NC 4 7A NC 5 VREF 8
To Target Board
R2
R3
10k 1%
24k 1%
Note:
The ICD 2 produces a VPP voltage greater than the maximum VPP specification of the PIC16F/LF1826/27.
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27.2 Low-Voltage Programming Entry Mode
FIGURE 27-2: ICD RJ-11 STYLE CONNECTOR INTERFACE
The Low-Voltage Programming Entry mode allows the PIC16F/LF1826/27 devices to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Word 2 is set to `1', the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to `0'. Entry into the Low-Voltage Programming Entry mode requires the following steps: 1. 2. MCLR is brought to VIL. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK.
VDD
ICSPDAT NC 246 ICSPCLK 13 5 VSS
VPP/MCLR
Target PC Board Bottom Side
Pin Description* 1 = VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect
Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. If low-voltage programming is enabled (LVP = 1), the MCLR Reset function is automatically enabled and cannot be disabled. See Section 7.3 "MCLR" for more information. The LVP bit can only be reprogrammed to `0' by using the High-Voltage Programming mode.
27.3
Common Programming Interfaces
Another connector often found in use with the PICkitTM programmers is a standard 6-pin header with 0.1 inch spacing. Refer to Figure 27-3.
Connection to a target device is typically done through an ICSPTM header. A commonly found connector on development tools is the RJ-11 in the 6P6C (6 pin, 6 connector) configuration. See Figure 27-2.
FIGURE 27-3:
PICKITTM STYLE CONNECTOR INTERFACE Pin 1 Indicator Pin Description*
1 2 3 4 5 6
1 = VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect
*
The 6-pin header (0.100" spacing) accepts 0.025" square pins.
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For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure 27-4 for more information.
FIGURE 27-4:
TYPICAL CONNECTION FOR ICSPTM PROGRAMMING
External Programming Signals VDD VPP VSS Data Clock
VDD
Device to be Programmed VDD MCLR/VPP VSS ICSPDAT ICSPCLK
*
*
*
To Normal Connections
* Isolation devices (as required).
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28.0 INSTRUCTION SET SUMMARY
28.1 Read-Modify-Write Operations
Each PIC16 instruction is a 14-bit word containing the operation code (opcode) and all required operands. The opcodes are broken into three broad categories. * Byte Oriented * Bit Oriented * Literal and Control The literal and control category contains the most varied instruction word format. Table 28-3 lists the instructions recognized by the MPASMTM assembler. All instructions are executed within a single instruction cycle, with the following exceptions, which may take two or three cycles: * Subroutine takes two cycles (CALL, CALLW) * Returns from interrupts or subroutines take two cycles (RETURN, RETLW, RETFIE) * Program branching takes two cycles (GOTO, BRA, BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) * One additional instruction cycle will be used when any instruction references an indirect file register and the file select register is pointing to program memory. One instruction cycle consists of 4 oscillator cycles; for an oscillator frequency of 4 MHz, this gives a nominal instruction execution rate of 1 MHz. All instruction examples use the format `0xhh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit. Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator `d'. A read operation is performed on a register even if the instruction writes to that register.
TABLE 28-1:
Field
f W b k x
OPCODE FIELD DESCRIPTIONS
Description
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. FSR or INDF number. (0-1) Pre-post increment-decrement mode selection
d
n mm
TABLE 28-2:
Field
PC TO C DC Z PD
ABBREVIATION DESCRIPTIONS
Description
Program Counter Time-out bit Carry bit Digit carry bit Zero bit Power-down bit
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FIGURE 28-1: GENERAL FORMAT FOR INSTRUCTIONS
0 Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 k (literal) 0 0
k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE k (literal) k = 11-bit immediate value MOVLP instruction only 13 OPCODE
0
7
6 k (literal)
0
k = 7-bit immediate value MOVLB instruction only 13 OPCODE k = 5-bit immediate value BRA instruction only 13 OPCODE
54 k (literal)
0
9
8 k (literal)
0
k = 9-bit immediate value FSR Offset instructions 13 OPCODE
7
6 n
5 k (literal)
0
n = appropriate FSR k = 6-bit immediate value FSR Increment instructions 13 OPCODE n = appropriate FSR m = 2-bit mode value OPCODE only 13 OPCODE
3
21 0 n m (mode)
0
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TABLE 28-3:
Mnemonic, Operands
PIC16F/LF1826/27 ENHANCED INSTRUCTION SET
Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift Clear f Clear W Complement f Decrement f Increment f Inclusive OR W with f Move f Move W to f Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Subtract with Borrow W from f Swap nibbles in f Exclusive OR W with f Decrement f, Skip if 0 Increment f, Skip if 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1(2) 1(2) 00 11 00 11 11 11 00 00 00 00 00 00 00 00 00 00 00 11 00 00 00 00 0111 1101 0101 0111 0101 0110 0001 0001 1001 0011 1010 0100 1000 0000 1101 1100 0010 1011 1110 0110 dfff dfff dfff dfff dfff dfff lfff 0000 dfff dfff dfff dfff dfff 1fff dfff dfff dfff dfff dfff dfff ffff ffff ffff ffff ffff ffff ffff 00xx ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C, DC, Z C, DC, Z Z C, Z C, Z C, Z Z Z Z Z Z Z Z C C C, DC, Z C, DC, Z Z 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1, 2 1, 2
BYTE ORIENTED SKIP OPERATIONS DECFSZ INCFSZ 1011 dfff ffff 1111 dfff ffff
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF f, b f, b Bit Clear f Bit Set f 1 1 01 01 00bb bfff ffff 01bb bfff ffff 2 2
BIT-ORIENTED SKIP OPERATIONS BTFSC BTFSS ADDLW ANDLW IORLW MOVLB MOVLP MOVLW SUBLW XORLW f, b f, b k k k k k k k k Bit Test f, Skip if Clear Bit Test f, Skip if Set Add literal and W AND literal with W Inclusive OR literal with W Move literal to BSR Move literal to PCLATH Move literal to W Subtract W from literal Exclusive OR literal with W 1 (2) 1 (2) 1 1 1 1 1 1 1 1 01 01 11 11 11 00 11 11 11 11 10bb bfff ffff 11bb bfff ffff 1110 1001 1000 0000 0001 0000 1100 1010 kkkk kkkk kkkk 001k 1kkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C, DC, Z Z Z 1, 2 1, 2
LITERAL OPERATIONS
C, DC, Z Z
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle.
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TABLE 28-3:
Mnemonic, Operands
PIC16F/LF1826/27 ENHANCED INSTRUCTION SET (CONTINUED)
Description Cycles 14-Bit Opcode MSb 11 00 10 00 10 00 11 00 00 00 00 00 00 00 11 00 11 00 11 001k 0000 0kkk 0000 1kkk 0000 0100 0000 0000 0000 0000 0000 0000 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 0000 0110 0000 0110 0000 0110 0110 LSb kkkk 1011 kkkk 1010 kkkk 1001 kkkk 1000 0100 TO, PD 0000 0010 0001 0011 TO, PD 0fff Status Affected Notes
CONTROL OPERATIONS BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN CLRWDT NOP OPTION RESET SLEEP TRIS ADDFSR MOVIW k - k - k k k - - - - - - f n, k n mm k[n] n mm k[n] Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine Clear Watchdog Timer No Operation Load OPTION_REG register with W Software device Reset Go into Standby mode Load TRIS register with W Add Literal k to FSRn Move Indirect FSRn to W with pre/post inc/dec modifier, mm Move INDFn to W, Indexed Indirect. Move W to Indirect FSRn with pre/post inc/dec modifier, mm Move W to INDFn, Indexed Indirect. 2 2 2 2 2 2 2 2 INHERENT OPERATIONS 1 1 1 1 1 1 1 1 1 1 1
C-COMPILER OPTIMIZED 0001 0nkk kkkk 0000 0001 0nmm Z kkkk 1111 0nkk 1nmm Z 0000 0001 kkkk 1111 1nkk 2, 3 2 2, 3 2
MOVWI
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. 3: See Table in the MOVIW and MOVWI instruction descriptions.
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28.2 Instruction Descriptions
Add Literal to FSRn
[ label ] ADDFSR FSRn, k -32 k 31 n [ 0, 1] FSR(n) + k FSR(n) None The signed 6-bit literal `k' is added to the contents of the FSRnH:FSRnL register pair. FSRn is limited to the range 0000h FFFFh. Moving beyond these bounds will cause the FSR to wrap around.
ADDFSR
Syntax: Operands: Operation: Status Affected: Description:
ANDLW
Syntax: Operands: Operation: Status Affected: Description:
AND literal with W
[ label ] ANDLW 0 k 255 (W) .AND. (k) (W) Z The contents of W register are AND'ed with the eight-bit literal `k'. The result is placed in the W register. k
ADDLW
Syntax: Operands: Operation: Status Affected: Description:
Add literal and W
[ label ] ADDLW 0 k 255 (W) + k (W) C, DC, Z The contents of the W register are added to the eight-bit literal `k' and the result is placed in the W register. k
ANDWF
Syntax: Operands: Operation: Status Affected: Description:
AND W with f
[ label ] ANDWF 0 f 127 d 0,1 (W) .AND. (f) (destination) Z AND the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
ADDWF
Syntax: Operands: Operation: Status Affected: Description:
Add W and f
[ label ] ADDWF 0 f 127 d 0,1 (W) + (f) (destination) C, DC, Z Add the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
ASRF
Syntax: Operands: Operation:
Arithmetic Right Shift
[ label ] ASRF 0 f 127 d [0,1] (f<7>) dest<7> (f<7:1>) dest<6:0>, (f<0>) C, C, Z The contents of register `f' are shifted one bit to the right through the Carry flag. The MSb remains unchanged. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f'. register f C f {,d}
Status Affected: Description:
ADDWFC
Syntax: Operands: Operation: Status Affected: Description:
ADD W and CARRY bit to f
[ label ] ADDWFC 0 f 127 d [0,1] (W) + (f) + (C) dest C, DC, Z Add W, the Carry flag and data memory location `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in data memory location `f'. f {,d}
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BCF
Syntax: Operands: Operation: Status Affected: Description:
Bit Clear f
[ label ] BCF 0 f 127 0b7 0 (f) None Bit `b' in register `f' is cleared. f,b
BTFSC
Syntax: Operands: Operation: Status Affected: Description:
Bit Test f, Skip if Clear
[ label ] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None If bit `b' in register `f' is `1', the next instruction is executed. If bit `b', in register `f', is `0', the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction.
BRA
Syntax: Operands: Operation: Status Affected: Description:
Relative Branch
[ label ] BRA label [ label ] BRA $+k -256 label - PC + 1 255 -256 k 255 (PC) + 1 + k PC None Add the signed 9-bit literal `k' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + k. This instruction is a two-cycle instruction. This branch has a limited range.
BTFSS
Syntax: Operands: Operation: Status Affected: Description:
Bit Test f, Skip if Set
[ label ] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None If bit `b' in register `f' is `0', the next instruction is executed. If bit `b' is `1', then the next instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction.
BRW
Syntax: Operands: Operation: Status Affected: Description:
Relative Branch with W
[ label ] BRW None (PC) + (W) PC None Add the contents of W (unsigned) to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + (W). This instruction is a two-cycle instruction.
BSF
Syntax: Operands: Operation: Status Affected: Description:
Bit Set f
[ label ] BSF 0 f 127 0b7 1 (f) None Bit `b' in register `f' is set. f,b
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CALL
Syntax: Operands: Operation:
Call Subroutine
[ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction.
CLRWDT
Syntax: Operands: Operation:
Clear Watchdog Timer
[ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
Status Affected: Description:
Status Affected: Description:
CALLW
Syntax: Operands: Operation:
Subroutine Call With W
[ label ] CALLW None (PC) +1 TOS, (W) PC<7:0>, (PCLATH<6:0>) PC<14:8> None Subroutine call with W. First, the return address (PC + 1) is pushed onto the return stack. Then, the contents of W is loaded into PC<7:0>, and the contents of PCLATH into PC<14:8>. CALLW is a two-cycle instruction.
COMF
Syntax: Operands: Operation: Status Affected: Description:
Complement f
[ label ] COMF 0 f 127 d [0,1] (f) (destination) Z The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. f,d
Status Affected: Description:
CLRF
Syntax: Operands: Operation: Status Affected: Description:
Clear f
[ label ] CLRF 0 f 127 00h (f) 1Z Z The contents of register `f' are cleared and the Z bit is set. f
DECF
Syntax: Operands: Operation: Status Affected: Description:
Decrement f
[ label ] DECF f,d 0 f 127 d [0,1] (f) - 1 (destination) Z Decrement register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'.
CLRW
Syntax: Operands: Operation: Status Affected: Description:
Clear W
[ label ] CLRW None 00h (W) 1Z Z W register is cleared. Zero bit (Z) is set.
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DECFSZ
Syntax: Operands: Operation: Status Affected: Description:
Decrement f, Skip if 0
[ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (destination); skip if result = 0 None The contents of register `f' are decremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', then a NOP is executed instead, making it a 2-cycle instruction.
INCFSZ
Syntax: Operands: Operation: Status Affected: Description:
Increment f, Skip if 0
[ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (destination), skip if result = 0 None The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', a NOP is executed instead, making it a 2-cycle instruction.
GOTO
Syntax: Operands: Operation: Status Affected: Description:
Unconditional Branch
[ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction.
IORLW
Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR literal with W
[ label ] IORLW k 0 k 255 (W) .OR. k (W) Z The contents of the W register are OR'ed with the eight-bit literal `k'. The result is placed in the W register.
INCF
Syntax: Operands: Operation: Status Affected: Description:
Increment f
[ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (destination) Z The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
IORWF
Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR W with f
[ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (destination) Z Inclusive OR the W register with register `f'. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
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LSLF
Syntax: Operands: Operation:
Logical Left Shift
[ label ] LSLF 0 f 127 d [0,1] (f<7>) C (f<6:0>) dest<7:1> 0 dest<0> C, Z The contents of register `f' are shifted one bit to the left through the Carry flag. A `0' is shifted into the LSb. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f'. C register f 0 f {,d}
MOVF
Syntax: Operands: Operation: Status Affected: Description:
Move f
[ label ] MOVF f,d 0 f 127 d [0,1] (f) (dest) Z The contents of register f is moved to a destination dependent upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected. 1 1 MOVF FSR, 0 After Instruction W = value in FSR register Z=1
Status Affected: Description:
Words: Cycles: Example:
LSRF
Syntax: Operands: Operation:
Logical Right Shift
[ label ] LSLF 0 f 127 d [0,1] 0 dest<7> (f<7:1>) dest<6:0>, (f<0>) C, C, Z The contents of register `f' are shifted one bit to the right through the Carry flag. A `0' is shifted into the MSb. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f'. 0 register f C f {,d}
Status Affected: Description:
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MOVIW
Syntax:
Move INDFn to W
[ label ] MOVIW ++FSRn [ label ] MOVIW --FSRn [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn] [ label ] MOVIW FSRn n [0,1] mm [00, 01, 10, 11]. -32 k 31 If not present, k = 0. INDFn W Effective address is determined by * FSR + 1 (preincrement) * FSR - 1 (predecrement) * FSR + k (relative offset) After the Move, the FSR value will be either: * FSR + 1 (all increments) * FSR - 1 (all decrements) * Unchanged Z Syntax ++FSRn --FSRn FSRn++ FSRn-mm 00 01 10 11
MOVLP
Syntax: Operands: Operation: Status Affected: Description:
Move literal to PCLATH
[ label ] MOVLP k 0 k 127 k PCLATH None The seven-bit literal `k' is loaded into the PCLATH register.
Operands:
Operation:
MOVLW
Syntax: Operands: Operation: Status Affected: Description:
Move literal to W
[ label ] k (W) None The eight-bit literal `k' is loaded into W register. The "don't cares" will assemble as `0's. 1 1 MOVLW 0x5A 0x5A After Instruction W= MOVLW k 0 k 255
Status Affected: Mode Preincrement Predecrement Postincrement Postdecrement Description:
Words: Cycles: Example:
MOVWF
Syntax: Operands: Operation: Status Affected: Description: Words: Cycles: Example:
Move W to f
[ label ] (W) (f) None Move data from W register to register `f'. 1 1 MOVWF OPTION = = = = 0xFF 0x4F 0x4F 0x4F Before Instruction OPTION W After Instruction OPTION W MOVWF f 0 f 127
This instruction is used to move data between W and one of the indirect registers (INDFn). Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it. Note: The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the FSRn. FSRn is limited to the range 0000h FFFFh. Incrementing/decrementing it beyond these bounds will cause it to wrap around. The increment/decrement operation on FSRn WILL NOT affect any Status bits.
MOVLB
Syntax: Operands: Operation: Status Affected: Description:
Move literal to BSR
[ label ] MOVLB k 0 k 15 k BSR None The five-bit literal `k' is loaded into the Bank Select Register (BSR).
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MOVWI
Syntax:
Move W to INDFn
[ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn [ label ] MOVWI FSRn++ [ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn] [ label ] MOVWI FSRn n [0,1] mm [00, 01, 10, 11]. -32 k 31 If not present, k = 0. W INDFn Effective address is determined by * FSR + 1 (preincrement) * FSR - 1 (predecrement) * FSR + k (relative offset) After the Move, the FSR value will be either: * FSR + 1 (all increments) * FSR - 1 (all decrements) Unchanged None Syntax ++FSRn --FSRn FSRn++ FSRn-mm 00 01 10 11
NOP
Syntax: Operands: Operation: Status Affected: Description: Words: Cycles: Example:
No Operation
[ label ] None No operation None No operation. 1 1 NOP NOP
Operands:
Operation:
OPTION
Syntax: Operands: Operation: Status Affected: Description:
Load OPTION_REG Register with W
[ label ] OPTION None (W) OPTION_REG None Move data from W register to OPTION_REG register.
Status Affected: Mode Preincrement Predecrement Postincrement Postdecrement Description:
RESET
Syntax: Operands: Operation: Status Affected: Description:
Software Reset
[ label ] RESET None Execute a device Reset. Resets the nRI flag of the PCON register. None This instruction provides a way to execute a hardware Reset by software.
This instruction is used to move data between W and one of the indirect registers (INDFn). Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it. Note: The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the FSRn. FSRn is limited to the range 0000h FFFFh. Incrementing/decrementing it beyond these bounds will cause it to wrap around. The increment/decrement operation on FSRn WILL NOT affect any Status bits.
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RETFIE
Syntax: Operands: Operation: Status Affected: Description:
Return from Interrupt
[ label ] None TOS PC, 1 GIE None Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. 1 2 RETFIE After Interrupt PC = GIE = TOS 1 RETFIE
RETURN
Syntax: Operands: Operation: Status Affected: Description:
Return from Subroutine
[ label ] None TOS PC None Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. RETURN
Words: Cycles: Example:
RETLW
Syntax: Operands: Operation: Status Affected: Description:
Return with literal in W
[ label ] RETLW k 0 k 255 k (W); TOS PC None The W register is loaded with the eight bit literal `k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. 1 2 CALL TABLE;W contains table ;offset value * ;W now has table value * * ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; * * * RETLW kn ; End of table Before Instruction W= After Instruction W=
RLF
Syntax: Operands: Operation: Status Affected: Description:
Rotate Left f through Carry
[ label ] 0 f 127 d [0,1] See description below C The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is stored back in register `f'. C Register f RLF f,d
Words: Cycles: Example:
Words: Cycles: Example:
1 1 RLF REG1,0 = = = = = 1110 0110 0 1110 0110 1100 1100 1 Before Instruction REG1 C After Instruction REG1 W C
TABLE
0x07 value of k8
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RRF
Syntax: Operands: Operation: Status Affected: Description:
Rotate Right f through Carry
[ label ] RRF f,d 0 f 127 d [0,1] See description below C The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. C Register f
SUBLW
Syntax: Operands: Operation: Status Affected: Description:
Subtract W from literal
[ label ] SUBLW k 0 k 255 k - (W) W) C, DC, Z The W register is subtracted (2's complement method) from the eight-bit literal `k'. The result is placed in the W register.
C=0 C=1 DC = 0 DC = 1
Wk Wk W<3:0> k<3:0> W<3:0> k<3:0>
SLEEP
Syntax: Operands: Operation:
Enter Sleep mode
[ label ] None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD The power-down Status bit, PD is cleared. Time-out Status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. SLEEP
SUBWF
Syntax: Operands: Operation: Status Affected: Description:
Subtract W from f
[ label ] SUBWF f,d 0 f 127 d [0,1] (f) - (W) destination) C, DC, Z Subtract (2's complement method) W register from register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f.
Status Affected: Description:
C=0 C=1 DC = 0 DC = 1
Wf Wf W<3:0> f<3:0> W<3:0> f<3:0>
SUBWFB
Syntax: Operands: Operation: Status Affected: Description:
Subtract W from f with Borrow
SUBWFB
0 f 127 d [0,1] (f) - (W) - (B) dest C, DC, Z Subtract W and the BORROW flag (CARRY) from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'.
f {,d}
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SWAPF
Syntax: Operands: Operation: Status Affected: Description:
Swap Nibbles in f
[ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) None The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed in register `f'.
XORLW
Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR literal with W
[ label ] XORLW k 0 k 255 (W) .XOR. k W) Z The contents of the W register are XOR'ed with the eight-bit literal `k'. The result is placed in the W register.
TRIS
Syntax: Operands: Operation: Status Affected: Description:
Load TRIS Register with W
[ label ] TRIS f 5f7 (W) TRIS register `f' None Move data from W register to TRIS register. When `f' = 5, TRISA is loaded. When `f' = 6, TRISB is loaded.
XORWF
Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR W with f
[ label ] XORWF f,d 0 f 127 d [0,1] (W) .XOR. (f) destination) Z Exclusive OR the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'.
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29.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings()
Ambient temperature under bias....................................................................................................... -40C to +125C Storage temperature ........................................................................................................................ -65C to +150C Voltage on VDD with respect to VSS, PIC16F1826/27 ........................................................................ -0.3V to +6.5V Voltage on VDD with respect to VSS, PIC16LF1826/27 ...................................................................... -0.3V to +4.0V Voltage on MCLR with respect to Vss ................................................................................................. -0.3V to +9.0V Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V) Total power dissipation(1) ............................................................................................................................... 800 mW Maximum current out of VSS pin ...................................................................................................................... 95 mA Maximum current into VDD pin ......................................................................................................................... 70 mA Clamp current, IK (VPIN < 0 or VPIN > VDD)20 mA Maximum output current sunk by any I/O pin.................................................................................................... 25 mA Maximum output current sourced by any I/O pin .............................................................................................. 25 mA Maximum current sunk by all ports(2), -40C TA +85C for industrial ........................................................ 200 mA Maximum current sunk by all ports(2), -40C TA +125C for extended........................................................ 90 mA Maximum current sourced by all ports(2), 40C TA +85C for industrial ................................................... 140 mA Maximum current sourced by all ports(2), -40C TA +125C for extended................................................... 65 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL). NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability.
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PIC16F/LF1826/27
FIGURE 29-1:
5.5
PIC16F1826/27 VOLTAGE FREQUENCY GRAPH, -40C TA +125C
VDD (V) 2.5 1.8 0 4 10 Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 29-1 for each Oscillator mode's supported frequencies.
16
32
FIGURE 29-2:
PIC16LF1826/27 VOLTAGE FREQUENCY GRAPH, -40C TA +125C
VDD (V)
3.6
2.5
1.8 0 4 10 Frequency (MHz) 16 32
Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 29-1 for each Oscillator mode's supported frequencies.
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FIGURE 29-3:
125 5% 85 Temperature (C) 3% 60
HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE
25
2%
0 -20 -40 1.8 2.0 2.5 3.0 3.5 5% 4.0 VDD (V) 4.5 5.0 5.5
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29.1 DC Characteristics: PIC16F/LF1826/27-I/E (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Supply Voltage PIC16LF1826/27 D001 D002* D002* VPOR* VPORR* VDR PIC16F1826/27 RAM Data Retention Voltage(1) PIC16LF1826/27 PIC16F1826/27 Power-on Reset Release Voltage Power-on Reset Rearm Voltage PIC16LF1826/27 PIC16F1826/27 D003 VADFVR Fixed Voltage Reference Voltage for ADC, Initial Accuracy -- -- -7 -8 -7 -8 -7 -8 -11 -11 -11 -11 -11 -11 -- -- 0.05 0.8 1.7 -- -- -- -- -- -- -- -- -- -- -- -- -130 0.270 -- -- -- 6 6 6 6 6 6 7 7 7 7 7 7 -- -- -- V V % Device in Sleep mode Device in Sleep mode 1.024V, VDD 2.5V, 85C (NOTE 3) 1.024V, VDD 2.5V, 125C (NOTE 3) 2.048V, VDD 2.5V, 85C 2.048V, VDD 2.5V, 125C 4.096V, VDD 4.75V, 85C 4.096V, VDD 4.75V, 125C 1.024V, VDD 2.5V, 85C 1.024V, VDD 2.5V, 125C 2.048V, VDD 2.5V, 85C 2.048V, VDD 2.5V, 125C 4.096V, VDD 4.75V, 85C 4.096V, VDD 4.75V, 125C 1.5 1.7 -- -- -- 1.6 -- -- -- V V V Device in Sleep mode Device in Sleep mode 1.8 2.3 1.8 2.3 -- -- -- -- 3.6 3.6 5.5 5.5 V V V V FOSC 16 MHz: FOSC 32 MHz (NOTE 2) FOSC 16 MHz: FOSC 32 MHz (NOTE 2) Min. Typ Max. Units Conditions
PIC16LF1826/27
PIC16F1826/27 Param. No. D001 Sym. VDD
D003A
VCDAFVR
Fixed Voltage Reference Voltage for Comparator and DAC, Initial Accuracy
%
D003C* TCVFVR D003D* VFVR/ VIN D004* * Note SVDD
Temperature Coefficient, Fixed Voltage Reference Line Regulation, Fixed Voltage Reference VDD Rise Rate to ensure internal Power-on Reset signal
ppm/ C %/V V/ms See Section 7.1 "Power-on Reset (POR)" for details.
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2: PLL required for 32 MHz operation. 3: For proper operation, the minimum value of the ADC positive voltage reference must be 1.8V or greater. When selecting the FVR or the VREF+ pin as the source of the ADC positive voltage reference, be aware that the voltage must be 1.8V or greater.
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FIGURE 29-4:
VDD VPOR VPORR
POR AND POR REARM WITH SLOW RISING VDD
VSS NPOR
POR REARM VSS TVLOW(2) Note 1: 2: 3: TPOR(3)
When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical.
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29.2 DC Characteristics: PIC16F/LF1826/27-I/E (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. Typ Max. Units Conditions VDD Note
PIC16LF1826/27
PIC16F1826/27 Param No. Device Characteristics Supply Current (IDD)(1, 2) D010 -- -- -- -- D010 -- -- -- -- -- -- D011 D011 -- -- -- -- -- D012 D012 -- -- -- -- -- D013 D013 -- -- -- -- -- * Note 1: 2:
7.0 9.0 9.0 10.0 24 30 32 22 28 33 110 220 160 280 390 290 520 450 770 930 32 60 100 180 225
13 16 17 18 40 45 50 40 42 48 190 480 255 475 690 400 700 645 1100 1320 -- -- 180 310 350
A A A A A A A A A A A A A A A A A A A A A A A A A
1.8 3.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0
FOSC = 32 kHz LP Oscillator mode, -40C TA +85C FOSC = 32 kHz LP Oscillator mode, -40C TA +125C FOSC = 32 kHz LP Oscillator mode -40C TA +85C FOSC = 32 kHz LP Oscillator mode -40C TA +125C FOSC = 1 MHz XT Oscillator mode FOSC = 1 MHz XT Oscillator mode
FOSC = 4 MHz XT Oscillator mode FOSC = 4 MHz XT Oscillator mode
FOSC = 500 kHz EC Oscillator mode, Medium-power mode FOSC = 500 kHz EC Oscillator mode Low-power mode
3: 4: 5:
These parameters are characterized but not tested. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins as inputs, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 8 MHz internal RC oscillator with 4x PLL enabled. 8 MHz crystal oscillator with 4x PLL enabled. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k.
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29.2 DC Characteristics: PIC16F/LF1826/27-I/E (Industrial, Extended) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. Typ Max. Units Conditions VDD Note PIC16LF1826/27
PIC16F1826/27 Param No. Device Characteristics Supply Current (IDD)(1, 2) D014 -- -- D014 -- -- -- D015 D015 -- -- -- -- -- D016 D016 -- -- -- -- -- D017* D017* -- -- -- -- -- D018 D018 -- -- -- -- -- * Note 1: 2:
260 450 475 850 980 3.6 4.0 21 27 28 110 150 150 210 270 0.8 1.3 1.0 1.8 2.0 1.2 2.0 1.7 2.9 3.1
475 750 735 1200 1390 10 13 35 40 45 175 250 250 345 425 1.1 1.7 1.48 2.2 2.8 2.0 2.75 2.23 4.3 4.6
A A A A A A A A A A A A A A A mA mA mA mA mA mA mA mA mA mA
1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0
FOSC = 4 MHz EC Oscillator mode, Medium-power mode FOSC = 4 MHz EC Oscillator mode Medium-power mode FOSC = 31 kHz LFINTOSC mode FOSC = 31 kHz LFINTOSC mode
FOSC = 500 kHz MFINTOSC mode FOSC = 500 kHz MFINTOSC mode
FOSC = 8 MHz HFINTOSC mode FOSC = 8 MHz HFINTOSC mode
FOSC = 16 MHz HFINTOSC mode FOSC = 16 MHz HFINTOSC mode
3: 4: 5:
These parameters are characterized but not tested. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins as inputs, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 8 MHz internal RC oscillator with 4x PLL enabled. 8 MHz crystal oscillator with 4x PLL enabled. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k.
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29.2 DC Characteristics: PIC16F/LF1826/27-I/E (Industrial, Extended) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. Typ Max. Units Conditions VDD Note PIC16LF1826/27
PIC16F1826/27 Param No. Device Characteristics Supply Current (IDD)(1, 2) D019 D019 D020 D020 D021 D021 -- -- -- -- -- -- -- -- -- -- -- -- -- * Note 1: 2:
4.0 4.4 3.9 4.2 3.3 3.6 5.3 6.0 410 710 430 730 860
-- -- -- -- 7.0 7.5 7.3 8.0 560 990 695 1060 1350
mA mA mA mA mA mA mA mA A A A A A
3.0 3.6 3.0 5.0 3.0 3.6 3.0 5.0 1.8 3.0 1.8 3.0 5.0
FOSC = 32 MHz HFINTOSC mode (Note 3) FOSC = 32 MHz HFINTOSC mode (Note 3) FOSC = 32 MHz HS Oscillator mode (Note 4) FOSC = 32 MHz HS Oscillator mode (Note 4) FOSC = 4 MHz EXTRC mode (Note 5) FOSC = 4 MHz EXTRC mode (Note 5)
3: 4: 5:
These parameters are characterized but not tested. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins as inputs, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 8 MHz internal RC oscillator with 4x PLL enabled. 8 MHz crystal oscillator with 4x PLL enabled. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k.
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PIC16F/LF1826/27
29.3 DC Characteristics: PIC16F/LF1826/27-I/E (Power-Down)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. (IPD)(2) -- -- D022 -- -- -- D023 D023 -- -- -- -- -- D023A D023A -- -- -- -- -- D024 D024 D025 D025 -- -- -- -- -- -- -- -- D026 D026 -- -- -- -- -- * Legend: Note 1: 0.02 0.03 15 18 19 0.5 0.8 16 19 20 8.5 8.5 32 39 70 8.1 34 67 0.6 0.8 16 21 25 0.1 0.1 16 21 25 1.0 2.0 35 40 45 3.0 4.0 35 40 45 23 26 50 72 120 14 57 100 3.0 4.0 35 40 45 3.0 4.0 35 40 50 5.0 7.0 50 60 70 7.0 9.0 50 60 70 35 40 66 80 110 17 70 115 7.0 9.0 45 50 55 7.0 9.0 45 50 60 A A A A A A A A A A A A A A mA A A A A A A A A A A A A A 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 3.0 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 A/D Current (Note 1, Note 3), no conversion in progress A/D Current (Note 1, Note 3), no conversion in progress T1OSC Current (Note 1) T1OSC Current (Note 1) BOR Current (Note 1) BOR Current (Note 1) FVR current (Note 1) FVR current (Note 1) LPWDT Current (Note 1) LPWDT Current (Note 1) WDT, BOR, FVR, and T1OSC disabled, all Peripherals Inactive WDT, BOR, FVR, and T1OSC disabled, all Peripherals Inactive Typ Max. +85C Max. +125C Units Conditions VDD Note
PIC16LF1826/27
PIC16F1826/27 Param No.
Device Characteristics Power-down Base Current
D022
2: 3:
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. TBD = To Be Determined The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins set to inputs state and tied to VDD. A/D oscillator source is FRC.
2010 Microchip Technology Inc.
Preliminary
DS41391C-page 351
PIC16F/LF1826/27
29.3 DC Characteristics: PIC16F/LF1826/27-I/E (Power-Down) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min.
(2)
PIC16LF1826/27
PIC16F1826/27 Param No.
Device Characteristics
Typ
Max. +85C
Max. +125C
Units
Conditions VDD 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 Comparator Current, Low Power mode, one comparator enabled (Note 1) Comparator Current, Low Power mode, one comparator enabled (Note 1) Comparator Current, Low Power mode, two comparators enabled (Note 1) Comparator Current, Low Power mode, two comparators enabled (Note 1) Cap Sense High Power Oscillator mode (Note 1) Cap Sense High Power Oscillator mode (Note 1) Cap Sense Medium Power Oscillator mode (Note 1) Cap Sense Medium Power Oscillator mode (Note 1) Cap Sense Low Power Oscillator mode (Note 1) Cap Sense Low Power Oscillator mode (Note 1) Note A/D Current (Note 1, Note 3), conversion in progress A/D Current (Note 1, Note 3), conversion in progress
Power-down Base Current (IPD) D026A* D026A*
-- -- -- -- --
250 250 280 280 280 3.5 7 4.3 5.8 6.3 4.2 6 7.4 9.7 10.4 6 10 17 41 50 6.9 7.0 9.0 9.3 9.8 7.0 7.2 9.4 9.7 11.4
-- -- -- -- -- 6 10 16 19 22 8 12 18 24 27 10 14 28 58 70 11 12 20 21 22 12 13 21 22 23
-- -- -- -- -- 8 14 26 30 35 10 15 26 30 33 15 20 40 70 90 15 16 24 25 27 16 17 25 26 28
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
D027 D027
-- -- -- -- --
D027A D027A
-- -- -- -- --
D027B D027B
-- -- -- -- --
D028
-- --
D028
-- -- --
D028A
-- --
D028A
-- -- -- *
Legend: Note 1:
2: 3:
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. TBD = To Be Determined The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins set to inputs state and tied to VDD. A/D oscillator source is FRC.
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Preliminary
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PIC16F/LF1826/27
29.3 DC Characteristics: PIC16F/LF1826/27-I/E (Power-Down) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min.
(2)
PIC16LF1826/27
PIC16F1826/27 Param No.
Device Characteristics
Typ
Max. +85C
Max. +125C
Units
Conditions VDD 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 Note Comparator Current, High Power mode, one comparator enabled (Note 1) Comparator Current, High Power mode, one comparator enabled (Note 1) Comparator Current, High Power mode, two comparators enabled Comparator Current, High Power mode, two comparators enabled (Note 1)
Power-down Base Current (IPD) D028B
-- --
24 25 27 28 29 40 41 43 44 45
32 35 50 53 55 80 83 86 90 95
40 45 55 58 60 90 95 100 105 110
A A A A A A A A A A
D028B
-- -- --
D028C D028C
-- -- -- -- -- *
Legend: Note 1:
2: 3:
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. TBD = To Be Determined The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins set to inputs state and tied to VDD. A/D oscillator source is FRC.
2010 Microchip Technology Inc.
Preliminary
DS41391C-page 353
PIC16F/LF1826/27
29.4 DC Characteristics: PIC16F/LF1826/27-I/E
DC CHARACTERISTICS Param No. Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. Typ Max. Units Conditions
Sym. VIL
Characteristic Input Low Voltage I/O PORT: with TTL buffer with Schmitt Trigger buffer with I2CTM levels with SMBusTM levels
D030 D030A D031
-- -- -- -- -- -- --
-- -- -- -- -- -- -- --
0.8 0.15 VDD 0.2 VDD 0.3 VDD 0.8 0.2 VDD 0.3 VDD -- -- -- -- -- -- -- -- -- 125 1000 200 200 300
V V V V V V V
4.5V VDD 5.5V 1.8V VDD 4.5V 2.0V VDD 5.5V 2.7V VDD 5.5V
D032 D033 VIH D040 D040A D041
MCLR, OSC1 (RC mode)(1) OSC1 (HS mode) Input High Voltage I/O ports: with TTL buffer
2.0 0.25 VDD + 0.8
-- -- -- -- -- -- -- -- 5 5
V V V V V V V V nA nA nA
4.5V VDD 5.5V 1.8V VDD 4.5V 2.0V VDD 5.5V 2.7V VDD 5.5V
with Schmitt Trigger buffer with I2CTM levels with SMBusTM levels
0.8 VDD 0.7 VDD 2.1 0.8 VDD 0.7 VDD 0.9 VDD --
D042 D043A D043B IIL D060
MCLR OSC1 (HS mode) OSC1 (RC mode) Input Leakage Current(2) I/O ports
(Note 1) VSS VPIN VDD, Pin at highimpedance at 85C 125C VSS VPIN VDD at 85C VDD = 3.3V, VPIN = VSS VDD = 5.0V, VPIN = VSS IOL = 8mA, VDD = 5V IOL = 6mA, VDD = 3.3V IOL = 1.8mA, VDD = 1.8V
D061 IPUR D070* VOL D080
MCLR(3) Weak Pull-up Current
-- 25 25
50 100 140
A
Output Low Voltage(4) I/O ports -- -- 0.6 V
Legend:
*
Note 1: 2: 3: 4:
TBD = To Be Determined These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Including OSC2 in CLKOUT mode.
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Preliminary
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PIC16F/LF1826/27
29.4 DC Characteristics: PIC16F/LF1826/27-I/E (Continued)
DC CHARACTERISTICS Param No. D090 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. Typ Max. Units Conditions
Sym. VOH
Characteristic Output High Voltage(4) I/O ports
VDD - 0.7 Capacitive Loading Specs on Output Pins D101* COSC2 OSC2 pin --
--
--
V
IOH = 3.5mA, VDD = 5V IOH = 3mA, VDD = 3.3V IOH = 1mA, VDD = 1.8V In XT, HS and LP modes when external clock is used to drive OSC1
--
15
pF
D101A* CIO Legend:
All I/O pins
--
--
50
pF
*
Note 1: 2: 3: 4:
TBD = To Be Determined These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Including OSC2 in CLKOUT mode.
2010 Microchip Technology Inc.
Preliminary
DS41391C-page 355
PIC16F/LF1826/27
29.5 Memory Programming Requirements
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Characteristic Program Memory Programming Specifications D110 D111 D112
D113 VPEW
DC CHARACTERISTICS Param No. Sym.
Min.
Typ
Max.
Units
Conditions
VIHH IDDP
Voltage on MCLR/VPP/RA5 pin Supply Current during Programming
VDD for Bulk Erase VDD for Write or Row Erase
8.0 --
2.7 VDD min. -- --
-- --
-- -- --
9.0 10
VDD max. VDD max. 1.0 5.0
V mA
V V mA mA
(Note 3, Note 4)
D114 D115 D116 D117 D118 D119 D120
IPPPGM Current on MCLR/VPP during Erase/ Write IDDPGM Current on VDD during Erase/Write
Data EEPROM Memory ED VDRW TDEW Byte Endurance VDD for Read/Write Erase/Write Cycle Time 100K
VDD min. -- --
--
VDD max.
E/W V ms Year E/W
-40C to +85C
-- 40 1M
4.0 -- 10M
5.0 -- --
TRETD Characteristic Retention TREF Number of Total Erase/Write Cycles before Refresh(2) Program Flash Memory Cell Endurance VDD for Read Self-timed Write Cycle Time
Provided no other specifications are violated -40C to +85C
D121 D122 D123 D124
EP VPR TIW
10K
VDD min.
-- --
--
VDD max.
E/W V ms Year
-40C to +85C (Note 1)
-- 40
2 --
2.5 --
TRETD Characteristic Retention
Provided no other specifications are violated
Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Self-write and Block Erase. 2: Refer to Section 11.2 "Using the Data EEPROM" for a more detailed discussion on data EEPROM endurance. 3: Required only if single-supply programming is disabled. 4: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the ICD 2 VPP voltage must be placed between the ICD 2 and target system when programming or debugging with the ICD 2.
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Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1826/27
29.6 Thermal Considerations
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. TH01 Sym. JA Characteristic Thermal Resistance Junction to Ambient Typ. TBD TBD TBD TBD TBD TH02 JC Thermal Resistance Junction to Case TBD TBD TBD TBD TBD TH03 TH04 TH05 TH06 TH07 TJMAX PD PI/O PDER Maximum Junction Temperature Power Dissipation I/O Power Dissipation Derated Power 150 -- -- -- -- Units C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C W W W W PD = PINTERNAL + PI/O PINTERNAL = IDD x VDD(1) PI/O = (IOL * VOL) + (IOH * (VDD - VOH)) PDER = PDMAX (TJ - TA)/JA(2) Conditions 18-pin PDIP package 18-pin SOIC package 20-pin SSOP package 28-pin UQFN 4x4mm package 28-pin QFN 6x6mm package 18-pin SPDIP package 18-pin SOIC package 20-pin SSOP package 28-pin UQFN 4x4mm package 28-pin QFN 6x6mm package
PINTERNAL Internal Power Dissipation
Legend: TBD = To Be Determined Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature 3: TJ = Junction Temperature
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Preliminary
DS41391C-page 357
PIC16F/LF1826/27
29.7 Timing Parameter Symbology
The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDIx do SDO dt Data in io I/O PORT mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low
T
Time
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCKx SS T0CKI T1CKI WR
P R V Z
Period Rise Valid High-impedance
FIGURE 29-5:
LOAD CONDITIONS
Load Condition
Pin
CL VSS
Legend: CL = 50 pF for all pins, 15 pF for OSC2 output
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Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1826/27
29.8 AC Characteristics: PIC16F/LF1826/27-I/E
CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
FIGURE 29-6:
OSC1/CLKIN OS02 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OS04 OS04
OSC2/CLKOUT (CLKOUT Mode)
TABLE 29-1:
CLOCK OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. OS01 Sym. FOSC Characteristic External CLKIN Frequency(1) Min. DC DC DC Oscillator Frequency(1) -- 0.1 1 1 DC OS02 TOSC External CLKIN Period(1) 27 250 50 31.25 Oscillator Period(1) -- 250 50 250 OS03 OS04* TCY TosH, TosL TosR, TosF Instruction Cycle Time(1) External CLKIN High, External CLKIN Low External CLKIN Rise, External CLKIN Fall 125 2 100 20 OS05* 0 0 0 * Typ -- -- -- 32.768 -- -- -- -- -- -- -- -- 30.5 -- -- -- -- -- -- -- -- -- -- Max. 0.5 4 32 -- 4 4 20 4 -- 10,000 1,000 -- DC -- -- -- Units MHz MHz MHz kHz MHz MHz MHz MHz s ns ns ns s ns ns ns ns s ns ns ns ns ns Conditions EC Oscillator mode (low) EC Oscillator mode (medium) EC Oscillator mode (high) LP Oscillator mode XT Oscillator mode HS Oscillator mode, VDD 2.7V HS Oscillator mode, VDD > 2.7V RC Oscillator mode LP Oscillator mode XT Oscillator mode HS Oscillator mode EC Oscillator mode LP Oscillator mode XT Oscillator mode HS Oscillator mode RC Oscillator mode TCY = FOSC/4 LP oscillator XT oscillator HS oscillator LP oscillator XT oscillator HS oscillator
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices.
2010 Microchip Technology Inc.
Preliminary
DS41391C-page 359
PIC16F/LF1826/27
TABLE 29-2: OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. OS08 Sym. HFOSC Characteristic Internal Calibrated HFINTOSC Frequency(2) Freq. Tolerance 2% 3% 5% OS08A MFOSC Internal Calibrated MFINTOSC Frequency(2) 2% 3% 5% OS10* TIOSC ST HFINTOSC Wake-up from Sleep Start-up Time MFINTOSC Wake-up from Sleep Start-up Time * -- Min. -- -- -- -- -- -- -- Typ 16.0 16.0 16.0 500 500 500 5 Max. -- -- -- -- -- -- 8 Units MHz MHz MHz kHz kHz kHz s Conditions 0C TA +60C, VDD 2.5V 60C TA +85C, VDD 2.5V -40C TA +125C 0C TA +60C, VDD 2.5V 60C TA +85C, VDD 2.5V -40C TA +125C
--
--
20
30
s
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to the OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. 3: By design.
TABLE 29-3:
Param No. F10 F11 F12 F13* Sym.
PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.7V TO 5.5V)
Characteristic Min. 4 16 -- -0.25% Typ -- -- -- -- Max. 8 32 2 +0.25% Units MHz MHz ms % Conditions
FOSC Oscillator Frequency Range FSYS TRC CLK On-Chip VCO System Frequency PLL Start-up Time (Lock Time) CLKOUT Stability (Jitter)
* These parameters are characterized but not tested. Data in "Typ" column is at 3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1826/27
FIGURE 29-7:
Cycle
CLKOUT AND I/O TIMING
Write Q4 Fetch Q1 Read Q2 Execute Q3
FOSC OS11 CLKOUT OS19 OS13 I/O pin (Input) OS15 I/O pin (Output) Old Value OS18, OS19 OS14 New Value OS17 OS20 OS21 OS16 OS18 OS12
2010 Microchip Technology Inc.
Preliminary
DS41391C-page 361
PIC16F/LF1826/27
TABLE 29-4: CLKOUT AND I/O TIMING PARAMETERS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. OS11 OS12 OS13 OS14 OS15 OS16 OS17 OS18 OS19 Sym. TosH2ckL TckL2ioV TioV2ckH TosH2ioV TosH2ioI TioV2osH TioR TioF Characteristic FOSC to CLKOUT (1)
(1) (1)
Min. -- -- -- TOSC + 200 ns -- 50 20 -- -- -- -- 25 25
Typ -- -- -- -- 50 -- -- 40 15 28 15 -- --
Max. 70 72 20 -- 70* -- -- 72 32 55 30 -- --
Units ns ns ns ns ns ns ns ns ns ns ns
Conditions VDD = 3.3-5.0V VDD = 3.3-5.0V
TosH2ckH FOSC to CLKOUT
CLKOUT to Port out valid
Port input valid before CLKOUT(1) Fosc (Q1 cycle) to Port out valid Fosc (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to Fosc(Q2 cycle) (I/O in setup time) Port output rise time(2) Port output fall time(2)
VDD = 3.3-5.0V VDD = 3.3-5.0V
VDD = 1.8V VDD = 3.3-5.0V VDD = 1.8V VDD = 3.3-5.0V
INT pin input high or low time Interrupt-on-change new input level time * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. 2: Includes OSC2 in CLKOUT mode.
OS20* Tinp OS21* Tioc
FIGURE 29-8:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR PWRT Time-out OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 34 I/O pins Note 1: Asserted low. 31 34 33 32 30
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Preliminary
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PIC16F/LF1826/27
FIGURE 29-9:
VDD VBOR VBOR and VHYST
BROWN-OUT RESET TIMING AND CHARACTERISTICS
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
37
Reset (due to BOR)
33(1)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Word 1 is programmed to `0'. 2 ms delay if PWRTE = 0 and VREGEN = 1.
2010 Microchip Technology Inc.
Preliminary
DS41391C-page 363
PIC16F/LF1826/27
TABLE 29-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. 30 31 32 33* 34* 35 36* 37* * Note 1: Sym. TMCL Characteristic MCLR Pulse Width (low) Min. 2 5 10 -- 40 -- 2.38 1.80 0 1 Typ -- -- 18 1024 65 -- 2.5 1.9 25 3 Max. -- -- 27 -- 140 2.0 2.65 2.05 50 5 Units s s ms Conditions VDD = 3.3-5V, -40C to +85C VDD = 3.3-5V VDD = 3.3V-5V
TWDTLP Low-Power Watchdog Timer Time-out Period (No Prescaler) TOST TPWRT TIOZ VBOR VHYST Oscillator Start-up Timer Period(1), (2) Power-up Timer Period, PWRTE = 0 I/O high-impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Voltage Brown-out Reset Hysteresis
Tosc (Note 3) ms s V mV s BORV=2.5V BORV=1.9V -40C to +85C VDD VBOR
TBORDC Brown-out Reset DC Response Time
2: 3: 4:
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to the OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. By design. Period of the slower clock. To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended.
FIGURE 29-10:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI 40 42 41
T1CKI 45 47 TMR0 or TMR1 46 49
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Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1826/27
TABLE 29-6: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. 40* 41* 42* Sym. TT0H TT0L TT0P Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler Min. 0.5 TCY + 20 10 0.5 TCY + 20 10 Greater of: 20 or TCY + 40 N 0.5 TCY + 20 15 30 0.5 TCY + 20 15 30 Greater of: 30 or TCY + 40 N 60 32.4 2 TOSC Typ -- -- -- -- -- Max. -- -- -- -- -- Units ns ns ns ns ns N = prescale value (2, 4, ..., 256) Conditions
45*
TT1H
T1CKI High Synchronous, No Prescaler Time Synchronous, with Prescaler Asynchronous T1CKI Low Time Synchronous, No Prescaler Synchronous, with Prescaler Asynchronous
-- -- -- -- -- -- --
-- -- -- -- -- -- --
ns ns ns ns ns ns ns N = prescale value (1, 2, 4, 8)
46*
TT1L
47*
TT1P
T1CKI Input Synchronous Period Asynchronous
-- 32.768 --
-- 33.1 7 TOSC
ns kHz -- Timers in Sync mode
48 49* *
FT1
Timer1 Oscillator Input Frequency Range (oscillator enabled by setting bit T1OSCEN)
TCKEZTMR1 Delay from External Clock Edge to Timer Increment
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 29-11:
CAPTURE/COMPARE/PWM TIMINGS (CCP)
CCPx (Capture mode)
CC01 CC03 Note: Refer to Figure 29.5 for load conditions.
CC02
TABLE 29-7:
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param Sym. No. CC01* TccL CC02* TccH CC03* TccP * Characteristic CCPx Input Low Time CCPx Input High Time CCPx Input Period No Prescaler With Prescaler No Prescaler With Prescaler Min. 0.5TCY + 20 20 0.5TCY + 20 20 3TCY + 40 N Typ -- -- -- -- -- Max. -- -- -- -- -- Units ns ns ns ns ns N = prescale value (1, 4 or 16) Conditions
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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TABLE 29-8: PIC16F/LF1826/27 A/D CONVERTER (ADC) CHARACTERISTICS:
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param Sym. No. AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 * Note 1: 2: 3: 4: 5: NR EIL EDL Characteristic Resolution Integral Error Differential Error Min. -- -- -- -- -- 1.8 VSS -- Typ -- -- -- -- -- -- -- -- Max. 10 1.7 1 2 1.5 VDD VREF 50 Units bit LSb VREF = 3.0V LSb No missing codes VREF = 3.0V LSb VREF = 3.0V LSb VREF = 3.0V V V VREF = (VREF+ minus VREF-) (NOTE 5) Conditions
EOFF Offset Error EGN VAIN ZAIN Gain Error Full-Scale Range Recommended Impedance of Analog Voltage Source VREF Reference Voltage(3)
k Can go higher if external 0.01F capacitor is
present on input pin.
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Total Absolute Error includes integral, differential, offset and gain errors. The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. ADC VREF is from external VREF, VDD pin or FVR, whichever is selected as reference input. When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module. FVR voltage selected must be 2.048V or 4.096V.
TABLE 29-9:
PIC16F/LF1826/27 A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. Sym. Characteristic A/D Clock Period A/D Internal RC Oscillator Period AD131 TCNV Conversion Time (not including Acquisition Time)(1) Acquisition Time Min. 1.0 1.0 -- -- Typ -- 1.6 11 5.0 Max. 9.0 6.0 -- -- Units s s TAD s TOSC-based ADCS<1:0> = 11 (ADRC mode) Set GO/DONE bit to conversion complete Conditions
AD130* TAD
AD132* TACQ *
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The ADRES register may be read on the following TCY cycle.
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FIGURE 29-12: PIC16F/LF1826/27 A/D CONVERSION TIMING (NORMAL MODE)
1 TCY AD131 AD130 A/D CLK A/D Data ADRES ADIF GO Sample AD132 Sampling Stopped 7 6 OLD_DATA 5 4 3 2 1 0 NEW_DATA 1 TCY DONE BSF ADCON0, GO AD134 Q4
(TOSC/2(1))
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
FIGURE 29-13:
PIC16F/LF1826/27 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO AD134 Q4 A/D CLK A/D Data ADRES ADIF GO Sample AD132 Sampling Stopped 7 6 5 4 3 2 1 0 NEW_DATA 1 TCY DONE (TOSC/2 + TCY(1)) AD131 AD130 1 TCY
OLD_DATA
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
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TABLE 29-10: COMPARATOR SPECIFICATIONS
Operating Conditions: 1.8V < VDD < 5.5V, -40C < TA < +125C (unless otherwise stated). Param No. CM01 CM02 CM03 CM04A CM04B CM04C CM04D CM05 CM06 * Note 1: 2: TMC2OV TRESP Sym. VIOFF VICM CMRR Characteristics Input Offset Voltage Input Common Mode Voltage Common Mode Rejection Ratio Response Time Rising Edge Response Time Falling Edge Response Time Rising Edge Response Time Falling Edge Comparator Mode Change to Output Valid* Min. -- 0 -- -- -- -- -- -- -- Typ. 7.5 -- 50 400 200 1200 550 -- 65 Max. 60 VDD -- 800 400 -- -- 10 -- Units mV V dB ns ns ns ns s mV Note 2 High Power Mode, Note 1 High Power Mode, Note 1 Low Power Mode, Note 1 Low Power Mode, Note 1 Comments
CHYSTER Comparator Hysterisis
These parameters are characterized but not tested. Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. Comparator Hysteresis is available when the CxHYS bit of the CMxCON0 register is enabled.
TABLE 29-11: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS
Operating Conditions: 1.8V < VDD < 5.5V, -40C < TA < +125C (unless otherwise stated). Param No. DAC01* DAC02* DAC03* DAC04* Sym. CLSB CACC CR CST Characteristics Step Size(2) Absolute Accuracy Unit Resistor Value (R) Settling Time(1) Min. -- -- -- -- Typ. VDD/32 -- TBD -- Max. -- 1/2 -- 10 Units V LSb s Comments
* These parameters are characterized but not tested. Legend: TBD = To Be Determined Note 1: Settling time measured while DACR<4:0> transitions from `0000' to `1111'.
TABLE 29-12: PIC16F/LF1826/27 LOW DROPOUT (LDO) REGULATOR CHARACTERISTICS:
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param Sym. No. LD001 LD002 * Characteristic LDO Regulation Voltage LDO External Capacitor Min. -- 0.1 Typ 3.2 -- Max. -- 1 Units V F Conditions
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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FIGURE 29-14: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
CK US121 DT US120 Note: Refer to Figure 29-5 for load conditions. US122 US121
TABLE 29-13: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param. No. Symbol Characteristic 3.0-5.5V 1.8-5.5V 3.0-5.5V 1.8-5.5V 3.0-5.5V 1.8-5.5V Min. -- -- -- -- -- -- Max. 80 100 45 50 45 50 Units ns ns ns ns ns ns Conditions
US120 TCKH2DTV SYNC XMIT (Master and Slave) Clock high to data-out valid US121 TCKRF US122 TDTRF Clock out rise time and fall time (Master mode) Data-out rise time and fall time
FIGURE 29-15:
CK DT
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
US125
US126 Note: Refer to Figure 29-5 for load conditions.
TABLE 29-14: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param. No. Symbol Characteristic Min. 10 15 Max. -- -- Units ns ns Conditions
US125 TDTV2CKL SYNC RCV (Master and Slave) Data-hold before CK (DT hold time) US126 TCKL2DTL Data-hold after CK (DT hold time)
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FIGURE 29-16:
SSx SP70 SCKx (CKP = 0) SP71 SP72 SP78 SCKx (CKP = 1) SP79 SP80 SDOx MSb bit 6 - - - - - -1 SP75, SP76 SDIx MSb In SP74 SP73 Note: Refer to Figure 29-5 for load conditions. bit 6 - - - -1 LSb In LSb SP78 SP79
SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
FIGURE 29-17:
SSx
SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SP81 SCKx (CKP = 0) SP71 SP73 SCKx (CKP = 1) SP80 SP78 LSb SP72 SP79
SDOx
MSb
bit 6 - - - - - -1 SP75, SP76
SDIx
MSb In SP74
bit 6 - - - -1
LSb In
Note: Refer to Figure 29-5 for load conditions.
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FIGURE 29-18:
SSx SP70 SCKx (CKP = 0) SP71 SP72 SP78 SCKx (CKP = 1) SP79 SP80 SDOx MSb bit 6 - - - - - -1 SP75, SP76 SDIx MSb In SP74 SP73 Note: Refer to Figure 29-5 for load conditions. bit 6 - - - -1 LSb In LSb SP77 SP78 SP79 SP83
SPI SLAVE MODE TIMING (CKE = 0)
FIGURE 29-19:
SSx
SPI SLAVE MODE TIMING (CKE = 1)
SP82 SP70
SCKx (CKP = 0) SP71 SCKx (CKP = 1) SP80 SP72
SP83
SDOx
MSb
bit 6 - - - - - -1 SP75, SP76
LSb SP77
SDIx
MSb In SP74
bit 6 - - - -1
LSb In
Note: Refer to Figure 29-5 for load conditions.
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TABLE 29-15: SPI MODE REQUIREMENTS
Param No. Symbol Characteristic Min. TCY TCY + 20 TCY + 20 100 100 -- -- -- 10 -- -- -- -- -- Tcy -- 1.5TCY + 40 3.0-5.5V 1.8-5.5V 3.0-5.5V 1.8-5.5V Typ -- -- -- -- -- 10 25 10 -- 10 25 10 -- -- -- -- -- Max. Units Conditions -- -- -- -- -- 25 50 25 50 25 50 25 50 145 -- 50 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SP70* TSSL2SCH, SSx to SCKx or SCKx input TSSL2SCL SP71* TSCH SP72* TSCL SCKx input high time (Slave mode) SCKx input low time (Slave mode)
SP73* TDIV2SCH, Setup time of SDIx data input to SCKx edge TDIV2SCL SP74* TSCH2DIL, TSCL2DIL SP75* TDOR SP76* TDOF SP77* TSSH2DOZ SP78* TSCR SP79* TSCF Hold time of SDIx data input to SCKx edge SDO data output rise time SDOx data output fall time SSx to SDOx output high-impedance SCKx output rise time (Master mode) 3.0-5.5V 1.8-5.5V
SCKx output fall time (Master mode)
SP80* TSCH2DOV, SDOx data output valid after TSCL2DOV SCKx edge
SP81* TDOV2SCH, SDOx data output setup to SCKx edge TDOV2SCL SP82* TSSL2DOV SDOx data output valid after SS edge SP83* TSCH2SSH, SSx after SCKx edge TSCL2SSH
* These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 29-20:
I2CTM BUS START/STOP BITS TIMING
SCLx SP91 SP90 SDAx SP92 SP93
Start Condition Note: Refer to Figure 29-5 for load conditions.
Stop Condition
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FIGURE 29-21: I2CTM BUS DATA TIMING
SP103 SCLx SP100 SP101 SP102
SP90 SP91
SP106
SP107
SP92 SP110
SDAx In SP109 SDAx Out Note: Refer to Figure 29-5 for load conditions. SP109
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TABLE 29-16: I2CTM BUS DATA REQUIREMENTS
Param. No. Symbol Characteristic Clock high time 100 kHz mode 400 kHz mode SSPx module SP101* TLOW Clock low time 100 kHz mode 400 kHz mode SSPx module SP102* TR SDAx and SCLx rise time 100 kHz mode 400 kHz mode Min. 4.0 0.6 1.5TCY 4.7 1.3 1.5TCY -- 20 + 0.1CB -- 20 + 0.1CB 0 0 250 100 -- -- 4.7 1.3 -- Max. -- -- -- -- -- -- 1000 300 250 250 -- 0.9 -- -- 3500 -- -- -- 400 Units s s -- s s -- ns ns ns ns ns s ns ns ns ns s s pF Time the bus must be free before a new transmission can start (Note 1) (Note 2) CB is specified to be from 10-400 pF CB is specified to be from 10-400 pF Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz Conditions Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz
SP100* THIGH
SP103* TF
SDAx and SCLx fall 100 kHz mode time 400 kHz mode Data input hold time 100 kHz mode 400 kHz mode Data input setup time Output valid from clock Bus free time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode
SP106* THD:DAT SP107* TSU:DAT SP109* TAA SP110* TBUF
SP111 * Note 1: 2:
CB
Bus capacitive loading
These parameters are characterized but not tested. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I2CTM bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCLx signal. If such a device does stretch the low period of the SCLx signal, it must output the next data bit to the SDAx line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCLx line is released.
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TABLE 29-17: CAP SENSE OSCILLATOR SPECIFICATIONS
Param. No. CS01 Symbol ISRC Characteristic Current Source High Medium Low CS02 ISNK Current Sink High Medium Low CS03 CS04 CS05 VCTH VCTL Cap Threshold Cap Threshold High Medium Low Min. -3 -0.8 -0.1 2.5 0.6 0.1 -- -- 350 250 175 Typ -8 -1.5 -0.3 7.5 1.5 0.25 0.8 0.4 525 375 300 Max. -15 -3 -0.4 14 2.9 0.6 -- -- 725 500 425 Units A A A A A A mV mV mV mV mV Conditions
VCHYST CAP HYSTERISIS (VCTH - VCTL)
* These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 29-22:
CAP SENSE OSCILLATOR
VCTH
VCTL
ISRC Enabled
ISNK Enabled
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NOTES:
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30.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS
Graphs and charts are not available at this time.
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31.0 DEVELOPMENT SUPPORT
31.1
The PIC(R) microcontrollers and dsPIC(R) digital signal controllers are supported with a full range of software and hardware development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debuggers - MPLAB ICD 3 - PICkitTM 3 Debug Express * Device Programmers - PICkitTM 2 Programmer - MPLAB PM3 Device Programmer * Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either C or assembly) * One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.
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31.2 MPLAB C Compilers for Various Device Families 31.5 MPLINK Object Linker/ MPLIB Object Librarian
The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip's PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
31.3
HI-TECH C for Various Device Families
The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip's PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms.
31.6
MPLAB Assembler, Linker and Librarian for Various Device Families
31.4
MPASM Assembler
The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
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31.7 MPLAB SIM Software Simulator 31.9
The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
MPLAB ICD 3 In-Circuit Debugger System
MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC(R) Flash microcontrollers and dsPIC(R) DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers.
31.8
MPLAB REAL ICE In-Circuit Emulator System
31.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and programming of PIC(R) and dsPIC(R) Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial ProgrammingTM. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software.
MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.
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31.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express
The PICkitTM 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip's Flash families of microcontrollers. The full featured Windows(R) programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip's powerful MPLAB Integrated Development Environment (IDE) the PICkitTM 2 enables in-circuit debugging on most PIC(R) microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software.
31.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits
A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.
31.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications.
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32.0
32.1
PACKAGING INFORMATION
Package Marking Information
18-Lead PDIP
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC16F1826-I/P 1010017
18-Lead SOIC (.300")
XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
Example
PIC16C1826-I /SO 1010017
20-Lead SSOP XXXXXXXXXXX XXXXXXXXXXX YYWWNNN
Example PIC16F1827 -I/SS 1010017
28-Lead QFN/UQFN
Example
XXXXXXXX XXXXXXXX YYWWNNN
16F1827 /ML 1010017
Legend: XX...X Y YY WW NNN
e3
* Note:
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
*
Standard PICmicro(R) device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
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32.2 Package Details
The following sections give the technical details of the packages.
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Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
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Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
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APPENDIX A:
Revision A
Original release (06/2009)
DATA SHEET REVISION HISTORY
APPENDIX B:
MIGRATING FROM OTHER PIC(R) DEVICES
This section provides comparisons when migrating devices to the from other similar PIC(R) PIC16F/LF1826/27 family of devices.
Revision B (08/09)
Revised Tables 5-3, 6-2, 12-2, 12-3; Updated Electrical Specifications; Added UQFN Package; Added SOIC and QFN Land Patterns; Updated Product ID section.
B.1
PIC16F648A to PIC16F/LF1827
FEATURE COMPARISON
PIC16F648A PIC16F/LF1827 20 MHz 4K 256 256 10-bit 2/1 Y RB<7:0> RB<7:4> 2 1/0 N N 48 kHz or 4 MHz Y N 2/0 N 0 N N N N Y 32 MHz 4K 384 256 10-bit 4/1 Y RB<7:0>, RA5 RB<7:0>, Edge Selectable 2 0/2 Y Y 31 kHz 32 MHz Y Y 2/2 Y 2/0 Y Y Y Y Y Feature
TABLE B-1:
Max. Operating Speed Max. Program Memory (Words)
Revision C (06/10)
Updated Electrical Specification Enhanced Core Golden Chapters. and included
Max. SRAM (Bytes) Max. EEPROM (Bytes) A/D Resolution Timers (8/16-bit) Brown-out Reset Internal Pull-ups Interrupt-on-Change Comparator AUSART/EUSART Extended WDT Software Control Option of WDT/BOR INTOSC Frequencies Clock Switching Capacitive Sensing CCP/ECCP Enhanced PIC16 CPU MSSPx/SSPx Reference Clock Data Signal Modulator SR Latch Voltage Reference DAC
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INDEX
A
A/D Specifications............................................................ 366 Absolute Maximum Ratings .............................................. 343 AC Characteristics Industrial and Extended ............................................ 359 Load Conditions ........................................................ 358 ACKSTAT ......................................................................... 268 ACKSTAT Status Flag ...................................................... 268 ADC .................................................................................. 139 Acquisition Requirements ......................................... 149 Associated registers.................................................. 151 Block Diagram........................................................... 139 Calculating Acquisition Time..................................... 149 Channel Selection..................................................... 140 Configuration............................................................. 140 Configuring Interrupt ................................................. 144 Conversion Clock...................................................... 140 Conversion Procedure .............................................. 144 Internal Sampling Switch (RSS) IMPEDANCE .............. 149 Interrupts................................................................... 142 Operation .................................................................. 143 Operation During Sleep ............................................ 143 Port Configuration ..................................................... 140 Reference Voltage (VREF)......................................... 140 Source Impedance.................................................... 149 Special Event Trigger................................................ 143 Starting an A/D Conversion ...................................... 142 ADCON0 Register....................................................... 31, 145 ADCON1 Register....................................................... 31, 146 ADDFSR ........................................................................... 333 ADDWFC .......................................................................... 333 ADRESH Register............................................................... 31 ADRESH Register (ADFM = 0) ......................................... 147 ADRESH Register (ADFM = 1) ......................................... 148 ADRESL Register (ADFM = 0).......................................... 147 ADRESL Register (ADFM = 1).......................................... 148 Alternate Pin Function....................................................... 121 Analog-to-Digital Converter. See ADC ANSELA Register ............................................................. 125 ANSELB Register ............................................................. 130 APFCON0 Register........................................................... 122 APFCON1 Register........................................................... 122 Assembler MPASM Assembler................................................... 380 EUSART Receive ..................................................... 288 EUSART Transmit .................................................... 287 External RC Mode ...................................................... 59 Fail-Safe Clock Monitor (FSCM)................................. 67 Generic I/O Port........................................................ 121 Interrupt Logic............................................................. 85 On-Chip Reset Circuit................................................. 77 Peripheral Interrupt Logic ........................................... 86 PIC16F/LF1826/27 ..................................................... 12 PIC16F193X/LF193X ................................................. 18 PWM (Enhanced) ..................................................... 214 Resonator Operation .................................................. 58 Timer0 ...................................................................... 175 Timer1 ...................................................................... 179 Timer1 Gate.............................................. 184, 185, 186 Timer2/4/6 ................................................................ 191 Voltage Reference.................................................... 137 Voltage Reference Output Buffer Example .............. 156 BORCON Register.............................................................. 79 BRA .................................................................................. 334 Break Character (12-bit) Transmit and Receive ............... 307 Brown-out Reset (BOR)...................................................... 79 Specifications ........................................................... 364 Timing and Characteristics ....................................... 363
C
C Compilers MPLAB C18.............................................................. 380 CALL................................................................................. 335 CALLW ............................................................................. 335 Capacitive Sensing ........................................................... 317 Associated registers w/ Capacitive Sensing............. 321 Specifications ........................................................... 375 Capture Module. See Enhanced Capture/Compare/ PWM(ECCP) Capture/Compare/PWM ................................................... 205 Capture/Compare/PWM (CCP) Associated Registers w/ Capture ............................. 207 Associated Registers w/ Compare ........................... 209 Associated Registers w/ PWM ......................... 213, 227 Capture Mode........................................................... 206 CCPx Pin Configuration............................................ 206 Compare Mode......................................................... 208 CCPx Pin Configuration.................................... 208 Software Interrupt Mode ........................... 206, 208 Special Event Trigger ....................................... 208 Timer1 Mode Resource ............................ 206, 208 Prescaler .................................................................. 206 PWM Mode Duty Cycle ........................................................ 211 Effects of Reset ................................................ 213 Example PWM Frequencies and Resolutions, 20 MHZ ................................ 212 Example PWM Frequencies and Resolutions, 32 MHZ ................................ 212 Example PWM Frequencies and Resolutions, 8 MHz .................................. 212 Operation in Sleep Mode.................................. 213 Resolution ........................................................ 212 System Clock Frequency Changes .................. 213 PWM Operation ........................................................ 210 PWM Overview......................................................... 210 PWM Period ............................................................. 211 PWM Setup .............................................................. 211
B
BAUDCON Register.......................................................... 298 BF ............................................................................. 268, 270 BF Status Flag .......................................................... 268, 270 Block Diagram Capacitive Sensing ................................................... 317 Block Diagrams (CCP) Capture Mode Operation ............................... 206 ADC .......................................................................... 139 ADC Transfer Function ............................................. 150 Analog Input Model ........................................... 150, 171 CCP PWM................................................................. 210 Clock Source............................................................... 56 Comparator ............................................................... 166 Compare ................................................................... 208 Crystal Operation .................................................. 58, 59 Digital-to-Analog Converter (DAC)............................ 155
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CCP1CON Register ...................................................... 35, 36 CCPR1H Register ......................................................... 35, 36 CCPR1L Register.......................................................... 35, 36 CCPTMRS0 Register ........................................................ 229 CCPxAS Register.............................................................. 230 CCPxCON (ECCPx) Register ........................................... 228 CLKRCON Register ............................................................ 74 Clock Accuracy with Asynchronous Operation ................. 296 Clock Sources External Modes ........................................................... 57 EC ....................................................................... 57 HS ....................................................................... 57 LP........................................................................ 57 OST..................................................................... 58 RC....................................................................... 59 XT ....................................................................... 57 Internal Modes ............................................................ 60 HFINTOSC.......................................................... 60 Internal Oscillator Clock Switch Timing............... 62 LFINTOSC .......................................................... 61 MFINTOSC ......................................................... 60 Clock Switching................................................................... 64 CMOUT Register............................................................... 173 CMxCON0 Register .......................................................... 172 CMxCON1 Register .......................................................... 173 Code Examples A/D Conversion ......................................................... 144 Changing Between Capture Prescalers .................... 206 Initializing PORTA ..................................................... 123 Initializing PORTB ..................................................... 128 Write Verify ............................................................... 117 Writing to Flash Program Memory ............................ 115 Comparator Associated Registers ................................................ 174 Operation .................................................................. 165 Comparator Module .......................................................... 165 Cx Output State Versus Input Conditions ................. 168 Comparator Specifications ................................................ 368 Comparators C2OUT as T1 Gate ................................................... 181 Compare Module. See Enhanced Capture/Compare/ PWM (ECCP) CONFIG1 Register.............................................................. 50 CONFIG2 Register.............................................................. 52 CPSCON0 Register .......................................................... 320 CPSCON1 Register .......................................................... 321 Customer Change Notification Service ............................. 402 Customer Notification Service........................................... 402 Customer Support ............................................................. 402 Device Configuration .......................................................... 49 Code Protection .......................................................... 53 Configuration Word..................................................... 49 User ID ................................................................. 53, 54 Device Overview................................................. 11, 103, 106 Digital-to-Analog Converter (DAC) ................................... 153 Associated Registers ................................................ 158 Effects of a Reset ..................................................... 155 Specifications ........................................................... 368
E
ECCP/CCP. See Enhanced Capture/Compare/PWM EEADR Registers ............................................................. 107 EEADRH Registers........................................................... 107 EEADRL Register ............................................................. 118 EEADRL Registers ........................................................... 107 EECON1 Register..................................................... 107, 119 EECON2 Register..................................................... 107, 120 EEDATH Register............................................................. 118 EEDATL Register ............................................................. 118 EEPROM Data Memory Avoiding Spurious Write ........................................... 108 Write Verify ............................................................... 117 Effects of Reset PWM mode ............................................................... 213 Electrical Specifications .................................................... 343 Enhanced Capture/Compare/PWM (ECCP)..................... 205 Enhanced PWM Mode.............................................. 214 Auto-Restart ..................................................... 223 Auto-shutdown.................................................. 222 Direction Change in Full-Bridge Output Mode.. 220 Full-Bridge Application...................................... 218 Full-Bridge Mode .............................................. 218 Half-Bridge Application ..................................... 217 Half-Bridge Application Examples .................... 224 Half-Bridge Mode.............................................. 217 Output Relationships (Active-High and Active-Low)............................................... 215 Output Relationships Diagram.......................... 216 Programmable Dead Band Delay..................... 224 Shoot-through Current ...................................... 224 Start-up Considerations .................................... 226 Specifications ........................................................... 365 Enhanced Mid-range CPU.................................................. 17 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) .............................. 287 Errata .................................................................................... 9 EUSART ........................................................................... 287 Associated Registers Baud Rate Generator ....................................... 300 Asynchronous Mode ................................................. 289 12-bit Break Transmit and Receive .................. 307 Associated Registers Receive .................................................... 295 Transmit.................................................... 291 Auto-Wake-up on Break ................................... 305 Baud Rate Generator (BRG) ............................ 299 Clock Accuracy................................................. 296 Receiver ........................................................... 292 Setting up 9-bit Mode with Address Detect ...... 294 Transmitter ....................................................... 289 Baud Rate Generator (BRG) Auto Baud Rate Detect..................................... 304 Baud Rate Error, Calculating............................ 299 Baud Rates, Asynchronous Modes .................. 301 Formulas........................................................... 300
D
DACCON0 (Digital-to-Analog Converter Control 0) Register..................................................................... 157 DACCON1 (Digital-to-Analog Converter Control 1) Register..................................................................... 157 Data EEPROM Memory .................................................... 107 Associated Registers ................................................ 120 Code Protection ........................................................ 108 Reading..................................................................... 108 Writing ....................................................................... 108 Data Memory....................................................................... 22 DC and AC Characteristics ............................................... 377 DC Characteristics Extended and Industrial ............................................ 354 Industrial and Extended ............................................ 346 Development Support ....................................................... 379
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High Baud Rate Select (BRGH Bit) .................. 299 Synchronous Master Mode ............................... 308, 313 Associated Registers Receive..................................................... 312 Transmit.................................................... 310 Reception.......................................................... 311 Transmission .................................................... 308 Synchronous Slave Mode Associated Registers Receive..................................................... 314 Transmit.................................................... 313 Reception.......................................................... 314 Transmission .................................................... 313 Extended Instruction Set ADDFSR ................................................................... 333 LSRF ........................................................................ 337 MOVF ....................................................................... 337 MOVIW ..................................................................... 338 MOVLB ..................................................................... 338 MOVWI ..................................................................... 339 OPTION.................................................................... 339 Reset ........................................................................ 339 SUBWFB .................................................................. 341 TRIS ......................................................................... 342 BCF .......................................................................... 334 BSF........................................................................... 334 BTFSC...................................................................... 334 BTFSS ...................................................................... 334 CALL......................................................................... 335 CLRF ........................................................................ 335 CLRW ....................................................................... 335 CLRWDT .................................................................. 335 COMF ....................................................................... 335 DECF........................................................................ 335 DECFSZ ................................................................... 336 GOTO ....................................................................... 336 INCF ......................................................................... 336 INCFSZ..................................................................... 336 IORLW ...................................................................... 336 IORWF...................................................................... 336 MOVLW .................................................................... 338 MOVWF.................................................................... 338 NOP.......................................................................... 339 RETFIE..................................................................... 340 RETLW ..................................................................... 340 RETURN................................................................... 340 RLF........................................................................... 340 RRF .......................................................................... 341 SLEEP ...................................................................... 341 SUBLW..................................................................... 341 SUBWF..................................................................... 341 SWAPF..................................................................... 342 XORLW .................................................................... 342 XORWF .................................................................... 342 INTCON Register................................................................ 91 Internal Oscillator Block INTOSC Specifications ................................................... 360 Internal Sampling Switch (RSS) IMPEDANCE ...................... 149 Internet Address ............................................................... 402 Interrupt-On-Change......................................................... 133 Associated Registers................................................ 135 Interrupts ............................................................................ 85 ADC .......................................................................... 144 Associated registers w/ Interrupts .............................. 99 Configuration Word w/ Clock Sources........................ 71 Configuration Word w/ PORTA................................. 127 Configuration Word w/ Reference Clock Sources ...... 75 TMR1........................................................................ 183 INTOSC Specifications ..................................................... 360 IOCBF Register ................................................................ 134 IOCBN Register ................................................................ 134 IOCBP Register ................................................................ 134
F
Fail-Safe Clock Monitor....................................................... 67 Fail-Safe Condition Clearing ....................................... 67 Fail-Safe Detection ..................................................... 67 Fail-Safe Operation..................................................... 67 Reset or Wake-up from Sleep..................................... 67 Firmware Instructions........................................................ 329 Fixed Voltage Reference (FVR) Associated Registers ................................................ 138 Flash Program Memory .................................................... 107 Erasing...................................................................... 112 Modifying................................................................... 116 Writing....................................................................... 112 FSR Register .......... 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40 FVRCON (Fixed Voltage Reference Control) Register ..... 138
I
I2C Mode (MSSPx) Acknowledge Sequence Timing................................ 272 Bus Collision During a Repeated Start Condition ................... 277 During a Stop Condition.................................... 278 Effects of a Reset...................................................... 273 I2C Clock Rate w/BRG.............................................. 280 Master Mode Operation .......................................................... 264 Reception.......................................................... 270 Start Condition Timing .............................. 266, 267 Transmission .................................................... 268 Multi-Master Communication, Bus Collision and Arbitration .................................................. 273 Multi-Master Mode .................................................... 273 Read/Write Bit Information (R/W Bit) ........................ 249 Slave Mode Transmission .................................................... 254 Sleep Operation ........................................................ 273 Stop Condition Timing............................................... 272 INDF Register ......... 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40 Indirect Addressing ............................................................. 44 Instruction Format ............................................................. 330 Instruction Set ................................................................... 329 ADDLW ..................................................................... 333 ADDWF..................................................................... 333 ADDWFC .................................................................. 333 ANDLW ..................................................................... 333 ANDWF..................................................................... 333 BRA........................................................................... 334 CALL ......................................................................... 335 CALLW...................................................................... 335 LSLF ......................................................................... 337
L
LATA Register .................................................................. 124 LATB Register .................................................................. 129 Load Conditions................................................................ 358 LSLF ................................................................................. 337 LSRF ................................................................................ 337
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M
Master Synchronous Serial Port. See MSSPx MCLR .................................................................................. 80 Internal ........................................................................ 80 MDCARH Register ............................................................ 202 MDCARL Register............................................................. 203 MDCON Register .............................................................. 200 MDSRC Register............................................................... 201 Memory Organization.......................................................... 19 Data ............................................................................ 22 Program ...................................................................... 19 Microchip Internet Web Site .............................................. 402 Migrating from other PIC Microcontroller Devices............. 393 MOVIW.............................................................................. 338 MOVLB.............................................................................. 338 MOVWI.............................................................................. 339 MPLAB ASM30 Assembler, Linker, Librarian ................... 380 MPLAB Integrated Development Environment Software .. 379 MPLAB PM3 Device Programmer..................................... 382 MPLAB REAL ICE In-Circuit Emulator System................. 381 MPLINK Object Linker/MPLIB Object Librarian ................ 380 MSSPx .............................................................................. 233 I2C Mode ................................................................... 244 I2C Mode Operation .................................................. 246 SPI Mode .................................................................. 236 SSPxBUF Register ................................................... 239 SSPxSR Register...................................................... 239 PIE2 Register...................................................................... 93 PIE3 Register...................................................................... 94 PIE4 Register...................................................................... 95 Pin Diagram PIC16F/LF1826/27, 18-pin PDIP/SOIC ........................ 5 PIC16F/LF1826/27, 28-pin QFN/UQFN........................ 6 Pinout Descriptions PIC16F/LF1826/27 ..................................................... 13 PIR1 Register ............................................................... 30, 96 PIR2 Register ......................................................... 30, 31, 97 PIR3 Register ..................................................................... 98 PIR4 Register ..................................................................... 99 PORTA ............................................................................. 123 ANSELA Register ..................................................... 123 Associated Registers ................................................ 127 PORTA Register ................................................... 30, 32 Specifications ........................................................... 362 PORTA Register ............................................................... 124 PORTB ............................................................................. 128 Additional Pin Functions Weak Pull-up .................................................... 129 ANSELB Register ..................................................... 128 Associated Registers ................................................ 132 Interrupt-on-Change ................................................. 128 P1B/P1C/P1D.See Enhanced Capture/Compare/ PWM+ (ECCP+) ............................................... 128 Pin Descriptions and Diagrams ................................ 131 PORTB Register ................................................... 30, 32 PORTB Register ............................................................... 129 Power-Down Mode (Sleep)............................................... 101 Associated Registers ........................................ 102, 203 Power-on Reset .................................................................. 78 Power-up Time-out Sequence ............................................ 80 Power-up Timer (PWRT) .................................................... 78 Specifications ........................................................... 364 PR2 Register ................................................................ 30, 38 Precision Internal Oscillator Parameters .......................... 360 Program Memory ................................................................ 19 Map and Stack (PIC16F/LF1826) ............................... 20 Map and Stack (PIC16F/LF1826/27) .................... 19, 20 Programming, Device Instructions .................................... 329 PSTRxCON Register ........................................................ 232 PWM (ECCP Module) PWM Steering........................................................... 225 Steering Synchronization.......................................... 226 PWM Mode. See Enhanced Capture/Compare/PWM ...... 214 PWM Steering................................................................... 225 PWMxCON Register ......................................................... 231
O
OPCODE Field Descriptions ............................................. 329 OPTION ............................................................................ 339 OPTION Register .............................................................. 177 OSCCON Register .............................................................. 69 Oscillator Associated Registers .................................................. 71 Oscillator Module ................................................................ 55 ECH ............................................................................ 55 ECL ............................................................................. 55 ECM ............................................................................ 55 HS ............................................................................... 55 INTOSC ...................................................................... 55 LP................................................................................ 55 RC ............................................................................... 55 XT ............................................................................... 55 Oscillator Parameters........................................................ 360 Oscillator Specifications .................................................... 359 Oscillator Start-up Timer (OST) Specifications ............................................................ 364 Oscillator Switching Fail-Safe Clock Monitor............................................... 67 Two-Speed Clock Start-up .......................................... 65 OSCSTAT Register............................................................. 70 OSCTUNE Register ............................................................ 71
R
RCREG............................................................................. 294 RCREG Register ................................................................ 33 RCSTA Register ......................................................... 33, 297 Reader Response............................................................. 403 Read-Modify-Write Operations ......................................... 329 Reference Clock ................................................................. 73 Associated Registers .................................................. 75 Registers ADCON0 (ADC Control 0) ........................................ 145 ADCON1 (ADC Control 1) ........................................ 146 ADRESH (ADC Result High) with ADFM = 0) .......... 147 ADRESH (ADC Result High) with ADFM = 1) .......... 148 ADRESL (ADC Result Low) with ADFM = 0)............ 147 ADRESL (ADC Result Low) with ADFM = 1)............ 148 ANSELA (PORTA Analog Select)............................. 125 ANSELB (PORTB Analog Select)............................. 130
P
P1A/P1B/P1C/P1D.See Enhanced Capture/Compare/ PWM (ECCP) ............................................................ 214 Packaging ......................................................................... 383 Marking ..................................................................... 383 PDIP Details.............................................................. 384 PCL and PCLATH ............................................................... 18 PCL Register........... 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40 PCLATH Register.... 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40 PCON Register ............................................................. 31, 83 PIE1 Register ................................................................ 31, 92
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APFCON0 (Alternate Pin Function Control 0)........... 122 APFCON1 (Alternate Pin Function Control 1)........... 122 BAUDCON (Baud Rate Control) ............................... 298 BORCON Brown-out Reset Control)........................... 79 CCPTMRS0 (PWM Timer Selection Control 0) ........ 229 CCPxAS (CCPx Auto-Shutdown Control)................. 230 CCPxCON (ECCPx Control)..................................... 228 CLKRCON (Reference Clock Control)........................ 74 CMOUT (Comparator Output)................................... 173 CMxCON0 (Cx Control) ............................................ 172 CMxCON1 (Cx Control 1) ......................................... 173 Configuration Word 1 .................................................. 50 Configuration Word 2 .................................................. 52 CPSCON0 (Capacitive Sensing Control Register 0) 320 CPSCON1 (Capacitive Sensing Control Register 1) 321 DACCON0 ................................................................ 157 DACCON1 ................................................................ 157 EEADRL (EEPROM Address) .................................. 118 EECON1 (EEPROM Control 1)................................. 119 EECON2 (EEPROM Control 2)................................. 120 EEDATH (EEPROM Data)........................................ 118 EEDATL (EEPROM Data) ........................................ 118 FVRCON................................................................... 138 INTCON (Interrupt Control)......................................... 91 IOCBF (Interrupt-on-Change Flag) ........................... 134 IOCBN (Interrupt-on-Change Negative Edge) .......... 134 IOCBP (Interrupt-on-Change Positive Edge) ............ 134 LATA (Data Latch PORTA)....................................... 124 LATB (Data Latch PORTB)....................................... 129 MDCARH (Modulation High Carrier Control Register) ........................................................... 202 MDCARL (Modulation Low Carrier Control Register) 203 MDCON (Modulation Control Register) .................... 200 MDSRC (Modulation Source Control Register) ........ 201 OPTION_REG (OPTION) ......................................... 177 OSCCON (Oscillator Control) ..................................... 69 OSCSTAT (Oscillator Status) ..................................... 70 OSCTUNE (Oscillator Tuning) .................................... 71 PCON (Power Control Register) ................................. 83 PCON (Power Control) ............................................... 83 PIE1 (Peripheral Interrupt Enable 1)........................... 92 PIE2 (Peripheral Interrupt Enable 2)........................... 93 PIE3 (Peripheral Interrupt Enable 3)........................... 94 PIE4 (Peripheral Interrupt Enable 4)........................... 95 PIR1 (Peripheral Interrupt Register 1) ........................ 96 PIR2 (Peripheral Interrupt Request 2) ........................ 97 PIR3 (Peripheral Interrupt Request 3) ........................ 98 PIR4 (Peripheral Interrupt Request 4) ........................ 99 PORTA...................................................................... 124 PORTB...................................................................... 129 PSTRxCON (PWM Steering Control) ....................... 232 PWMxCON (Enhanced PWM Control) ..................... 231 RCREG ..................................................................... 304 RCSTA (Receive Status and Control)....................... 297 SPBRGH................................................................... 299 SPBRGL ................................................................... 299 Special Function, Summary ........................................ 30 SRCON0 (SR Latch Control 0) ................................. 161 SRCON1 (SR Latch Control 1) ................................. 162 SSPxADD (MSSPx Address and Baud Rate, I2C Mode) ......................................................... 286 SSPxCON1 (MSSPx Control 1) ................................ 283 SSPxCON2 (SSPx Control 2) ................................... 284 SSPxCON3 (SSPx Control 3) ................................... 285 SSPxMSK (SSPx Mask) ........................................... 286 SSPxSTAT (SSPx Status)........................................ 282 STATUS ..................................................................... 23 T1CON (Timer1 Control) .......................................... 187 T1GCON (Timer1 Gate Control)............................... 188 TRISA (Tri-State PORTA) ........................................ 124 TRISB (Tri-State PORTB) ........................................ 129 TXCON ..................................................................... 193 TXSTA (Transmit Status and Control)...................... 296 WDTCON (Watchdog Timer Control) ....................... 105 WPUB (Weak Pull-up PORTB)......................... 125, 130 Reset .......................................................................... 77, 339 Reset Instruction................................................................. 80 Resets ................................................................................ 77 Associated Registers.................................................. 84 Revision History................................................................ 393
S
Shoot-through Current ...................................................... 224 Software Simulator (MPLAB SIM) .................................... 381 SPBRG Register................................................................. 33 SPBRGH Register ............................................................ 299 SPBRGL Register............................................................. 299 Special Event Trigger ....................................................... 143 Special Function Registers (SFRs)..................................... 30 SPI Mode (MSSPx) Associated Registers................................................ 243 SPI Clock.................................................................. 239 SR Latch ........................................................................... 159 Associated registers w/ SR Latch............................. 163 SRCON0 Register ............................................................ 161 SRCON1 Register ............................................................ 162 SSP1ADD Register............................................................. 34 SSP1BUF Register ............................................................. 34 SSP1CON Register ............................................................ 34 SSP1CON2 Register .......................................................... 34 SSP1CON3 Register .......................................................... 34 SSP1MSK Register ............................................................ 34 SSP1STAT Register ........................................................... 34 SSP2ADD Register............................................................. 34 SSP2BUF Register ............................................................. 34 SSP2CON1 Register .......................................................... 34 SSP2CON2 Register .......................................................... 34 SSP2CON3 Register .......................................................... 34 SSP2MSK Register ............................................................ 34 SSP2STAT Register ........................................................... 34 SSPxADD Register........................................................... 286 SSPxCON1 Register ........................................................ 283 SSPxCON2 Register ........................................................ 284 SSPxCON3 Register ........................................................ 285 SSPxMSK Register........................................................... 286 SSPxOV ........................................................................... 270 SSPxOV Status Flag ........................................................ 270 SSPxSTAT Register ......................................................... 282 R/W Bit ..................................................................... 249 Stack................................................................................... 42 Accessing ................................................................... 42 Reset .......................................................................... 44 Stack Overflow/Underflow .................................................. 80 STATUS Register ............................................................... 23 SUBWFB .......................................................................... 341
T
T1CON Register ......................................................... 30, 187 T1GCON Register ............................................................ 188 T2CON Register ........................................................... 30, 38 Thermal Considerations.................................................... 357
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Timer0 ....................................................................... 175, 194 Associated Registers ................................................ 177 Operation .................................................................. 175 Specifications ............................................................ 365 Timer1 ............................................................................... 179 Associated registers.................................................. 189 Asynchronous Counter Mode ................................... 181 Reading and Writing ......................................... 181 Clock Source Selection ............................................. 180 Interrupt..................................................................... 183 Operation .................................................................. 180 Operation During Sleep ............................................ 183 Oscillator ................................................................... 181 Prescaler ................................................................... 181 Specifications ............................................................ 365 Timer1 Gate Selecting Source............................................... 181 TMR1H Register ....................................................... 179 TMR1L Register ........................................................ 179 Timer2 Associated registers.................................................. 194 Timer2/4/6 ......................................................................... 191 Associated registers.................................................. 194 Timers Timer1 T1CON.............................................................. 187 T1GCON ........................................................... 188 Timer2/4/6 TXCON ............................................................. 193 Timing Diagrams A/D Conversion ......................................................... 367 A/D Conversion (Sleep Mode) .................................. 367 Acknowledge Sequence ........................................... 272 Asynchronous Reception .......................................... 294 Asynchronous Transmission ..................................... 290 Asynchronous Transmission (Back to Back) ............ 290 Auto Wake-up Bit (WUE) During Normal Operation . 306 Auto Wake-up Bit (WUE) During Sleep .................... 306 Automatic Baud Rate Calibration .............................. 304 Baud Rate Generator with Clock Arbitration ............. 265 BRG Reset Due to SDA Arbitration During Start Condition........................................................... 276 Brown-out Reset (BOR) ............................................ 363 Brown-out Reset Situations ........................................ 79 Bus Collision During a Repeated Start Condition (Case 1) ............................................................ 277 Bus Collision During a Repeated Start Condition (Case 2) ............................................................ 277 Bus Collision During a Start Condition (SCL = 0) ..... 276 Bus Collision During a Stop Condition (Case 1) ....... 278 Bus Collision During a Stop Condition (Case 2) ....... 278 Bus Collision During Start Condition (SDA only) ...... 275 Bus Collision for Transmit and Acknowledge............ 274 CLKOUT and I/O....................................................... 361 Clock Synchronization .............................................. 262 Clock Timing ............................................................. 359 Comparator Output ................................................... 165 Enhanced Capture/Compare/PWM (ECCP) ............. 365 Fail-Safe Clock Monitor (FSCM) ................................. 68 First Start Bit Timing ................................................. 266 Full-Bridge PWM Output ........................................... 219 Half-Bridge PWM Output .................................. 217, 224 I2C Bus Data ............................................................. 373 I2C Bus Start/Stop Bits.............................................. 372 I2C Master Mode (7 or 10-Bit Transmission) ............ 269 I2C Master Mode (7-Bit Reception)........................... 271 I2C Stop Condition Receive or Transmit Mode......... 273 INT Pin Interrupt ......................................................... 89 Internal Oscillator Switch Timing ................................ 63 PWM Auto-shutdown ................................................ 223 Firmware Restart .............................................. 222 PWM Direction Change ............................................ 220 PWM Direction Change at Near 100% Duty Cycle... 221 PWM Output (Active-High) ....................................... 215 PWM Output (Active-Low) ........................................ 216 Repeat Start Condition ............................................. 267 Reset Start-up Sequence ........................................... 81 Reset, WDT, OST and Power-up Timer ................... 362 Send Break Character Sequence ............................. 307 SPI Master Mode (CKE = 1, SMP = 1) ..................... 370 SPI Mode (Master Mode).......................................... 239 SPI Slave Mode (CKE = 0) ....................................... 371 SPI Slave Mode (CKE = 1) ....................................... 371 Synchronous Reception (Master Mode, SREN) ....... 312 Synchronous Transmission ...................................... 309 Synchronous Transmission (Through TXEN) ........... 309 Timer0 and Timer1 External Clock ........................... 364 Timer1 Incrementing Edge ....................................... 183 Two Speed Start-up.................................................... 66 USART Synchronous Receive (Master/Slave) ......... 369 USART Synchronous Transmission (Master/Slave). 369 Wake-up from Interrupt............................................. 102 Timing Diagrams and Specifications PLL Clock ................................................................. 360 Timing Parameter Symbology .......................................... 358 Timing Requirements I2C Bus Data............................................................. 374 SPI Mode .................................................................. 372 TMR0 Register.................................................................... 30 TMR1H Register ................................................................. 30 TMR1L Register.................................................................. 30 TMR2 Register.............................................................. 30, 38 TRIS.................................................................................. 342 TRISA Register........................................................... 31, 124 TRISB ............................................................................... 128 TRISB Register........................................................... 31, 129 Two-Speed Clock Start-up Mode........................................ 65 TXCON (Timer2/4/6) Register .......................................... 193 TxCON Register ............................................................... 213 TXREG ............................................................................. 289 TXREG Register ................................................................. 33 TXSTA Register.......................................................... 33, 296 BRGH Bit .................................................................. 299
U
USART Synchronous Master Mode Requirements, Synchronous Receive .............. 369 Requirements, Synchronous Transmission...... 369 Timing Diagram, Synchronous Receive ........... 369 Timing Diagram, Synchronous Transmission... 369
V
VREF. SEE ADC Reference Voltage
W
Wake-up on Break ............................................................ 305 Wake-up Using Interrupts ................................................. 102 Watchdog Timer (WDT)...................................................... 80 Modes ....................................................................... 104 Specifications ........................................................... 364
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WCOL ....................................................... 265, 268, 270, 272 WCOL Status Flag .................................... 265, 268, 270, 272 WDTCON Register ........................................................... 105 WPUB Register ......................................................... 125, 130 Write Protection .................................................................. 53 WWW Address.................................................................. 402 WWW, On-Line Support ....................................................... 9
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NOTES:
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THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.
2010 Microchip Technology Inc.
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READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS41391C FAX: (______) _________ - _________
Device: PIC16F/LF1826/27 Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41391C-page 404
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2010 Microchip Technology Inc.
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PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a) b) Device: PIC16F1826(1), PIC16F1827(1), PIC16F1826T(2), PIC16F1827T(2); VDD range 1.8V to 5.5V PIC16LF1826(1), PIC16LF1827(1), PIC16LF1826T(2), PIC16LF1827T(2); VDD range 1.8V to 3.6V I E ML MV P SO SS = = = = = = -40C to +85C = -40C to +125C (Industrial) (Extended) c) PIC16F1826 - I/ML 301 = Industrial temp., QFN package, Extended VDD limits, QTP pattern #301. PIC16F1826 - I/P = Industrial temp., PDIP package, Extended VDD limits. PIC16F1827 - E/SS= Extended temp., SSOP package, normal VDD limits.
Temperature Range: Package:
Micro Lead Frame (QFN) 6x6 Micro Lead Frame (UQFN) 4x4 Plastic DIP SOIC SSOP
Note 1: 2:
F = Wide Voltage Range LF = Standard Voltage Range T = in tape and reel SOIC, SSOP, and QFN/UQFN packages only.
Pattern:
QTP, SQTP, Code or Special Requirements (blank otherwise)
2010 Microchip Technology Inc.
Preliminary
DS41391C-page 405
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
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EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
01/05/10
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2010 Microchip Technology Inc.

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